Brit chip company picks RISC-V for next-gen microcontrollers British chip company XMOS has revealed its latest xcore high-performance microcontrollers are to be built around the RISC-V open standard instruction set architecture, in the hopes of opening up the silicon to a wider range of embedded system designers. Unveiled at the RISC-V Summit in San Jose, which starts today, the fourth …
That won't stop them from selling out and walking off into the sunset with enough loot to live a comfortable life from there on in.
We see it time and time again. A Startup gets some traction (justified or hype) and in swoops a mage-corp and we never see or hear about that bit of tech again.
Sometimes that USP does appear years later in another product but far too often Startup CEOs are just looking for a way out the door with pockets and bank accounts stuffed full of loot.
Consider me jaded and have a drawer full of T-shirts saying, 'been there done that and all I got for it was this lousy T-Shirt'
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A bit of both, usually the skills needed to launch a successful startup are different from those needed to manage a large organisation, meaning either they get bored and want to start something else up and/or get asked to step aside by shareholders to make way for someone more focussed on process.
"Startup CEOs are just looking for a way out the door with pockets and bank accounts stuffed full of loot."
Well, for starters around 95% of startup CEOs end up bankrupt and back to square 1 with very little to show for years of blood, sweat and tears. So for those few who took a crazy idea and ran with it, and managed to build it up to a huge success (for a startup), would you want to have years more of grief to nurture your baby to be big enough to play with the big boys (again highly unlikely).
"Loot" is what pirates and thieves get away with. A CEO of a successful startup can rightly walk away with a full bank account because they bloody well worked their arses off for years and deserve it. It's not like most of them would retire anyway, you don't succeed without passion for what you do, they will most likely move on to the next thing they can contribute to.
I do miss the old days when there was actually a reasonable amount of choice between processor architectures. Nowadays it is all amd64, aarch64/arm64, and only very rarely anything else. I'm glad to see a newcomer shake things up, and if it takes misguided US meanderings about China to give the architecture a kick in the pants, then so be it.
As per usual, current US foreign policy is about to backfire on them very badly a decade down the road, if not sooner. There are a lot more nations with interest in RISC-V than China, and the Intel near-monopoly is on the way down, and with it, American control of the processor markets.
This is s tech publication not a right wing political rag, so I'm surprised about why an open source architecture would be able to control whom ever wants to use it.
Also surprised you haven't blamed Jewish people too, or as you call them the "World Economic Forum".
The forum needs a cnut badge that readers can assign to posts.
And WHAT ABOUT, oh the horror, also working with those terrorists who flattened Afghanistan and earlier Iraq and their civilian infrastructure was decimated.
RU bombs energy infra a bit and everyone is screaming "war crime!" Oh what a laugh. Let them be slaughtered, or is it forbidden because they are not brown/far/foreign/ragged?
So, they seem to have three “big ideas”: firstly, they reckon to produce a really powerful microcontroller while avoiding all the hardware complexity of performance cores by keeping it in-order scalar, and avoiding cache by effectively dropping the *per-thread* CPU clock to the floor, plus internal RAM. They make up the performance difference using hardware threads, to make a rather small silicon area look like a multicore.
Secondly they note that most microcontrollers spend their time spinning round a scheduling loop, so by hardware partitioning this avoids lots of the software overhead of task-swapping. And you get a large part of hard-real-time software time-and-space partitioning for reliability, for free. It’s quite a nice idea.
The third big idea is implementing bit-bashing I/O directly as CPU instructions. They *might* be right about that, specifically for the microcontroller market.
The main question is whether their market performance niche between microcontroller and multicore out-of-order really exists in practice. Essentially they need to *create* their own market, at a time when most chips are either significantly more or less powerful. But technically, this chip has several “simple” (=very smart indeed) neat solutions.
Yes and no; I mean upvote as I largely agree and it's certainly been brought into focus by its relatively humourless pandering to its intended audience rather than its actual one, but it's unfortunately hard to forget that it was frequently pretty bad during The Lewis Page Years. Back then it often published very polarising political stuff with zero tech content, and if that didn't annoy there was always his self-proclaimed military "expertise" which always boiled down to the same divisive "buy American" line. I'm not sure it entirely recovered from that era, but this phase of its existence is definitely not one of its finer moments.
I don't think that the reference back to Lewis Page is really relevant to the complaint in the comment you've replied to. Those were articles that had a political edge - and as you knew were familiar with Page's name (which used to appear next to the article on the front page) you could avoid or dive in at will.
However, this article is politics free.
No, the problem is that nowadays the comments always seem to get dragged back to politics, no matter how technical the article on its own is. Quite a few even make good points, relevant to the article, then suddenly end with a political snipe. A shame.
It seems to have escaped everyone’s notice on this forum, but XMOS have said they very specifically *didn’t* write or use RISCV core. Instead they used their existing *proprietary* core, which is RISC concept but not RISCV, which works functionally, has already been properly optimised using modern EDA toolsets, and has been tested in the field through multiple spins.
Since their CPU is RISC *concept*, it has all the basic instructions expected, ie a one-to-one mapping to the RISCV ISA. They just put a tiny preprocessor in front of their existing instruction decoder to swap a few bitfields around. They’ve not had to mess with a single gate of their working CPU. The bitfield swapper probably fits into a couple hundred gates. And that, kids, is the approach that a *professional* design team will take. Throw away all your open-source CPU shit, and use the only thing of value: outsourced support for compiler tool chain.
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