Re: MIDI Maze! @nautica
This insistence that you do not want a segmented model flies in the face of almost all modern processors.
This is because a segment model still exists in almost all modern processors, they're just not crippled like the 80286's model was.
The 80286 had, if I understand it correctly, a single segment register that had to be set up each time you needed to move to another part of the address space.
But comparing this to, say, Power, VAX, PDP11, IBM/370, Sparc and I believe 68010, the memory management of all of these still has the concept of memory segments. Indeed, they're fundamental to the implementation of virtual address spaces that modern multi-processing capable processors provide.
The difference is that there are multiple segment registers in all of the architectures that I've listed that allow the complete program address space to be mapped simultaneously. The virtual address spaces are implemented by setting up the segment registers to map the contiguous virtual address space into different addresses in the real address space of the processor. So a program thinks it's running in a flat 32 or 64 bit address space while the actual memory could be scattered all over the physical address space, even out of sequence, and with 'holes' that aren't backed up by physical memory.
One advantage of this is that the system can preserve the complete address space of a program on a context switch by saving the contents of the segment registers when pre-empted, and restoring when you get back to execute. And systems like the 370, PDP11 and VAX had a different set of segment registers when in supervisor or privileged mode meaning that you didn't even have to save the segment registers when you crossed into kernel space to handle an interrupt or service a system call, and the Sparc had register rings to do something similar.
And in the case of the PDP11, which had a 16 bit process address space mapped into a physical 18 or 22 bit address space (depending on the model), it allowed the system to have more memory than a process could use, and I'm sure that the PDP11 was not the only processor that implemented this trick. In fact, I believe that late model 32 bit Pentium processors also used something similar with PAE. And now you have multiple registers sets and register renaming, including the memory segment registers that can be used to provide even more sets without having to save registers.
In most cases, this allows you to treat the virtual address space as a flat address space for the purposes of writing programs, but even in architectures like Power, there are a range of addressing modes that work within a single segment, meaning that it's not flat for all addressing modes (in fact IBM used this in-segment offset addressing mode to allow shared libraries to be position independent in AIX, at least in the 32 bit Power implementations).
When working in IBM's AIX System Support Centre shortly after the RS/6000 was launched, I remember taking a call from a developer who started by saying "Is the RS/6000 processor still a segemented architecture?", to which I started answering "Well, yes, but it's not like the Intel 80286 because..." at which point the person at the other end said "Well that's just rubbish!" and hung up the phone, without bothering to listen to why it was different. This has stuck in my memory for over thirty years. I often wonder whether the anonymous person (because he didn't even say who he was, or what company he was from) ever got to the point where he realized he had drawn a hasty conclusion.
But getting back to when the IBM PC was being designed, even if they had chosen a 68000, they could not have had virtual address spaces, because the 68000 did not have a built in memory management unit, that was provided by the 68451, which was a few years later than the 68000 (and was flawed so much that Sun built their own memory management unit for the early 68000 based Sun 1 and 2 systems).
Biting the hand that feeds IT
