Amazing
This article manages to include a lot of words, but somehow completely avoids defining what's different about the startup's tech.
Silicon Valley startup Eliyan thinks its technology for enabling chiplet-based designs can best those from semiconductor giants Intel and TSMC by providing better performance, higher efficiency, fewer manufacturing issues, and more supply chain options. The upstart announced on Tuesday that it has raised $40 million from …
The chiplet interconnect method - "BoW"?
Farjadrad claims NuLink can accomplish these feats by connecting chiplets through high-density wires that travel within the organic substrate, which serves as the foundation of the system-on-package. This is in contrast to CoWoS, which uses a connective layer between the chiplets and substrate called the silicon interposer, and to EMIB, which connects chiplets via silicon bridges embedded within the substrate.
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Farjadrad says the interconnect tech is considered a superset of bunch-of-wires (BoW) – another die-to-die interface he developed while running a previous startup, Aquantia. BoW is now the chiplet interconnect scheme used by the Open Compute Project – the organization founded by Meta that steers open source datacenter and chip designs for the world's largest consumers of servers.
"Bunch of wires" sounds like the interconnect Apple is using, i.e. a variant of one of TSMC's offerings though that extra layer would make it more expensive. At least "bunch of wires" is how I would define Apple's M1 Ultra with more than 10,000 I/Os connecting the two M1 Max dies, and the M2 Max will be able to connect four dies together which would be 30,000 I/Os.
I don't think the startup has fully revealed that yet.
We'll have to see if this is real or just hype, but this field is pretty new so I expect there are plenty of avenues to try not all of which TSMC and Intel have explored, so maybe they've found something better.
If so I imagine they will be snapped up by TSMC, or one of their major customers like Apple or Nvidia who wants a competitive advantage.
Same as 1960 tech, only smaller for those who remember. The main problem is faulty chiplets doing faulty speculation, or just no initializing memory/registers allowing leakages. The public seems to ignore defective cpus. Buslines have noise and crosstalk. If you shrink to 5mn then you are closer - less noise. Apple gets it, and have worked out better compromises with the shrinkage. But nobody seems to remember ICL(Fujitsu) SUN Computer, and DEC, loving fat rich busses.