Rambus offers chip designers a drop-in PCIe 6.0 subsystem

While PCIe 5.0 continues to gain traction, Rambus has made available a PCIe 6.0 Interface Subsystem for incorporation in third-party hardware. It comprises PHY and controller blocks, with the PHY also supporting the latest CXL 3.0 specifications. The PCIe 6.0 specifications were released by the PCI-SIG consortium early this …

[Pirate Dave]

Rambus is still around? I guess some prayers never get answered... His Noodly Holiness is probably busy with other things and can't honor every single prayer for CEO ass-cancer.

Are they still a bunch of dicks?

[Tom Womack]

In what form does this PCIe 6.0 Interface Subsystem come? Any PHY with fast SERDES is basically analogue design and very deeply process-specific at the moment, it would be nice to know what processes the blocks are available for.

(the press release at Rambus just says 'on advanced process nodes', it would be an interesting insight into the fabrication industry to know whether that includes Intel Integrated Foundry Services and Samsung's offerings, or just means TSMC N5 and N3)

[neilo]

Patent Troll

The patent troll rears its ugly head after so many years.

[Anonymous Coward]

Like leviathans, grey beards rise from their slumber

faces twisted, eyes burning

pointing gnarled fingers

"We remember"

[Vometia has insomnia. Again.]

"Oops, did we forget to mention that bit?"

I assume the most novel part of this design will turn out to be the concealment of numerous patented technologies that carry hefty licence fees.

[neilo]

Re: "Oops, did we forget to mention that bit?"

Closely followed by the discovery that the much-ballyhooed memory technology is slow, inefficient junk that needs a bigger heatsink than an NVidia GPU.