The assertion of this article is that a common low-level RISC could be shared between an ARM and AMD64 implementation.
AMD has actually done this already, between the 29k and the K5.
Details on AMD SPARC:
"Based on the seminal Berkeley RISC, the 29k added a number of significant improvements. They were, for a time, the most popular RISC chips on the market.. Berkeley RISC-derived designs is the concept of register windows... In the original Berkeley design, SPARC, and i960, the windows were fixed in size.... It was here that the 29000 differed from these earlier designs, using a variable window size."
K5 reused previous RISC elements:
"The K5 was based upon an internal highly parallel Am29000 RISC processor architecture with an x86 decoding front-end."
So... here we go again?