First details on TSMC's 2nm node: Chipmaker reveals nanosheet transistors

Taiwanese chipmaker TSMC has revealed details of its much anticipated 2nm production process node – set to arrive in 2025 – which will use a nanosheet transistor architecture, as well as enhancements to its 3nm technology. The newer generations of silicon semiconductor chips are expected to bring about increases in speed and …

[Mishak]

$44 billion in investment

And no calls for bribes subsidies?

[John Savard]

Isn't this...

the same as GAAFET, which we heard of some time ago?

[Tom 7]

Re: Isn't this...

The order to leave an Irish pub?

[Bartholomew]

The future will be bars!

So a Stacked nanosheet FET is similar to a FinFET but with a much large surface area per unit volume between the source and the gate. The big difference is the larger number of steps involved in creating Stacked nanosheet FET's. So the result of the larger surface area is that the voltage can be lower and the switching speed increased.

Makes you wonder what will be next, will the individual ribbons be split into some kind of 3D horizontal bar grid to further increase the surface area.

I raise a pint to the amazing engineering involved in getting these things to work.

[stathis_d]

My i386DX@25MHz was 40 microns tech. This is 2nm

Back in 2010 this was the theoretical limit of transistor shrinking.