MIPS architecture is at the core of a lot of Cisco gear. Wondering if C is looking RISC-V for new platforms.......
MIPS is back, but this time the company is bringing processors to market based on the RISC-V open instruction set architecture, rather than the MIPS architecture the chip designer is synonymous with. The current incarnation* of MIPS proclaimed its entry to the RISC-V market with a preview of the first products in its new …
I know, from a purely logical level, that a poorly designed website which can not handle a spike in traffic has nothing whatsoever to do with their products, but it never looks good. Every single link on their website gives the above message, which is not really the first impression that a company selling "superscalar performance" should be giving to anyone. If you do not have your own global Internet Infrastructure there is always CDN's (Content Delivery Network), some are free, but most are cheap.
It is not really clear which markets they want to address. Auto/Aerospace/Rail is very much different from computing or networking. The bread-and-butter control unit has integrated SRAM in the range of a few Mbytes; while computing uses thousands of times more external DRAM. Control units need very specialized A/D, D/A, pwm, watchdog, crypto peripery. Must all be on a single chip or it will be too big and too expensive.
Then you need support from Lauterbach (debugger) and Vector Informatik (AUTOSAR operating system) to be viable in automotive.
I suspect STM, NXP, Infineon, TI, Japan are so much entrenched in control units that MIPS does not stand a chance as a newcomer.
Computing and automotive are very much different, even though they sometimes use the same CPU cores (ARM and PowerPC, VAX come to mind).
Of all design companies, MIPS is probably the best placed to exploit RISC-V... it's said that the two ISAs are fairly similar, so a) the transition would be relatively easy and b) there's the opportunity to use legacy designs or design ideas/philosophy. It was interesting to read the line about them having some proprietary extensions - obviously there's nothing stopping them from doing that - I guess they'll be "translations" of instructions from the original MIPS ISA...?
The scaling idea in particular sounds interesting - that it's relatively easy to tailor for... any?... use case?
According to legend, MIPS III was adapted by NEC to create the R4300i used in Nintendo 64 (while PlayStation used the R3000). Later on, Toshiba adapted MIPS IV to create the R5900 used by PlayStation 2. Sony and Microsoft went to PowerPC for PlayStation 3 / Xbox 360, then gave up all that nonsense and went with AMD x86-64 for PlayStation 4 / Xbox One (also PlayStation 5 / Xbox One X).
I guess the promise of RISC is faster, lower power calculations, as long as they are kept within their simpler instruction set. It made sense up until AMD adapted x86 rich instruction set to 64 bit, high clock rate, and low cost. I forget why they went to PowerPC for the PS3/X360 generation though. Apple had been using PowerPC for its OSX desktop computers up until G5 in 2006, then they, too, went to x86-64 (intel).
I forget why they went to PowerPC for the PS3/X360 generation though.
For Sony it was Hubris, for MS it was just good sense.
Sony were riding high on the back of the PS2, and the world wasn't quite as standardised back then, so they decided to design their own CPU for the next Playstation, called the Cell.
This was developed by Sony, Toshiba and IBM, and contained a Power PC based core, with 6 extra scalar processing units. (This was back in the day before a GPU was doing this kind of general purpose computing).
The story goes that MS went to IBM when they were looking for the CPU for the next XBox (the power PC stuff wasn't slow remember), and IBM said 'Well... we're working on something like that for Sony...'
So the PowerPC core from the cell ended up forming the basis for the 3 core power PC CPU at the heart of the XBox 360.
More info here...
"The RISC-V architecture also provides for customization in the form of user defined instructions (UDIs), and MIPS said this would be useful in many high-end applications, while also keeping full compatibility with standard RISC-V development tools and software libraries."
And how long until we have a dozen processors, from different companies, all offering their own custom things (look, this one helps with mining!), all of which are totally incompatible with each other?
After a brief stint with opening up the MIPS ISA under similar terms as RISC V (and OpenPower), it seems the shambling zombie that was MIPS has now finally disintegrated. Not too surprising.
Still seeing a lot of MIPS SoCs in older networking and AV gear, but everything produced the past 15 years or so appears to use ARM instead. Guess MIPS was a fun ISA while it lasted, but it's hard to fight against x86, ARM and Power on multiple fronts when your marketshare drops year over year.
John Hennessy founded MIPS.
David Patterson created the Berkely RISC processor that became SPARC, (RAID) and now the RISC-V CPU.
As long-term collaborators, they have the seminal textbook on CPUs: Computer Organization and Design MIPS Edition: The Hardware/Software Interface.
Perhaps Hennessy's creation has realised that its own v2 is the RISC-V, hence dumping the v1 stuff.
Hennessy's MIPS project at Stanford (eventually spun out into the company MIPS) and Patterson's RISC project at Berkeley were both funded under DARPA's VLSI grant program, starting around 1980.
Both also took inspiration from IBM's 801 project, which started in 1974, and Tannenbaum's 1978 paper showing most applications used only a small number of the instructions provided by the CISC architectures that dominated in that era.
IBM's 801 evolved into the ROMP CPU (begun '77, running '81, public demo '84), which became the CPU for the PC RT (1986); and the RIOS / POWER architecture (development '82-'89, available 1990). John Cocke was probably the most influential figure in RISC development at IBM, though there were certainly many others, such as Phil Hester.
There was a lot of cross-influence. Tannenbaum's study and others made an argument that was sufficiently compelling to drive parallel development on RISC architectures in a number of places.
I have implemented SOCs around arm mips and recently risc-v.
ARM has the best documentation and support and defines the most aspects of the architecture, such as cache coherency, interrupt handlers, etc.
Both Arm and MIPS have incredibly large software libraries and tooling pre-available, mature, known and trusted.
Apart from grabbing headlines I really don't see the value of risc-V for this company.
RISC-V is still an instruction set and requires tons of other technologies to enable actual designs.