RISC-V keeps its head down amid global chip war

On the one hand, it's all positive on the RISC-V front, with its open-source ethos driving folks around the world, from the US and Europe to China and Russia, to collaborate on improving and boosting the specification. On the other hand, the borderless nature of the emerging instruction set architecture – which is royalty-free …

[steelpillow]

Sorry, what was the problem again?

So we are looking at an open-sourced future which is international in scope. Does Linux have problems because there are Chinese and Russian distros as well as US and European? Will RISC-V create open-source issues where none currently exist? Might open-source hardware designs implementing RISC-V become a thing? Might commercial companies seek to add closed-source goodies to their flavours? Might they even don their national-flag underpants while they are at it? Sorry, what was the problem specific to open-sourcing an instruction set? I can't seem to remember it.

[Pascal Monett]

Re: Sorry, what was the problem again?

The problem is that the US is once again trying to find ways to demonize China.

They're going to use open-source tools just like we can ? The bastards !

[Tom 7]

Re: Sorry, what was the problem again?

Open Source isnt the problem then - its the US.

[Anonymous Coward]

Re: Sorry, what was the problem again?

> Open Source isnt the problem then - its the US.

Considering the fact that the RISC-V ISA was donated to the world by an American - namely David Patterson, perhaps you should consider STFU.

[Slovrtux]

Re: Sorry, what was the problem again?

We are talking about how old politics see the open source movment. The fact that the creator of the risc-v is American is not relevant ... We make fun of American politics ... Not American people, those are 2 different entities. And if you come with the argument that American elect their representatives, just keep inind that their is not one country in the world where the population isvtotally satisfied with there gouvernant. To rephrase what was said before "open source is not the problem ... US gouvernement his"

[Anonymous Coward]

Re: Sorry, what was the problem again?

> The fact that the creator of the risc-v is American is not relevant [ ... ]

Actually, it very much is relevant.

The RISC-V ISA was invented by David Patterson at University of California, Berkeley. He originally developed it as a teaching tool.

That institution of higher education receives grant money from the State of California, and from the US Federal Government.

The RISC-V ISA itself draws on Patterson's previous experience inventing the original SPARC ISA in the '80's. That project also received major funding from the US Federal Government.

So: the RISC-V ISA was developed with significant financial subsidies from US Taxpayers.

Next time you so generously decide that the fact that we invent things isn't relevant, maybe you should spend 15 seconds thinking about who paid for it, and who made it possible in the first place.

[martinusher]

Re: Sorry, what was the problem again?

>So: the RISC-V ISA was developed with significant financial subsidies from US Taxpayers.

Yes, but that was 50 years ago. Every other major invention has undergone exactly the same democratization process. One country develops it, others adopt it and continue developing it, its the way the world works.

My complaint is that we're not developing anything like this these days. We are developing technologies but most of our efforts seem to be going into stopping others from developing rather than enabling our own people to move ahead.

[Anonymous Coward]

Re: Sorry, what was the problem again?

> Yes, but that was 50 years ago.

So? Did David Patterson invent this ISA or not? Did we - US Taxpayers - pay for it or not?

Where does this notion of collective right to appropriating someone else's accomplishments come from? Jealousy? Jealousy because someone else didn't think of it? Or because someone else wasn't smart enough to see the potential of the discovery, and didn't support it?

Individual accomplishments are never democratized. You may want to think that they are, but they're not. That's just delusional.

This is nothing short of football / soccer fan mentality. Just because you were in the rafters, yelling and blowing your vuvuzela, doesn't mean you scored the goal. Nor does it mean that you contributed anything to that goal. Someone else - who was playing on the pitch - scored that goal. Deal with it.

Shakespeare wrote Hamlet. Not someone else, even though it happened centuries ago. And Hamlet still isn't a collective work.

[martinusher]

Re: Sorry, what was the problem again?

Here's the problem. Very few inventions are totally unique, they're all a derivative of work that has come before and often they relay on seemingly unrelated work before they become viable. So, for example, the idea behind a RISC instruction set was well known before the 1980s (when it was formally invented) but had to wait for its 'time' for other technologies to mature for the concept to be viable.

The CDC (Control Data Corporation) 6600 is probably the first implementation of the reduced instruction set concept and itself could be considered to be a development inspired by the Atlas. The concepts are there but are limited by having to implement the logic in transistors or, at best, small scale integration.

(Speaking as a US taxpayer myself there are pressing issues about the abuse of US taxpayer funded IP, especially by the pharmaceutical industry, that the government avoids. The federal government is also not being entirely honest about the cost of the trade war with China and how it reflects on current levels of inflation. Secretary Raimondo is wasting a salary tilting at windmills.)

[Bruce Hoult]

Re: Sorry, what was the problem again?

Well, no David Patterson didn't invent RISC-V.

He was there in a kind of supervisory role, but in fact the main supervisor was Englishman Krste Asanovic (who, as you might imagine from his name, has recent roots in Eastern Europe), with most of the grunt work done by American Andrew Waterman, and Korean Yunsup Lee (I think Yunsup was born in the US but he speaks Korean fluently and has grandparents there).

That was the initial specification for the basic integer and floating point instructions corresponding to C's built in operators, between 2010 and 2015.

Since 2015 the ISA has been extended in a number of directions by international working groups with participation by experts from every part of the globe.

[Anonymous Coward]

Re: Sorry, what was the problem again?

> the main supervisor was Englishman Krste Asanovic

Oh, but of course it was a Brit. If it's not a Brit, it's someone from China.

https://riscv.org/news/2018/03/david-patterson-vice-chair-board-risc-v-foundation-receives-prestigious-2017-acm-m-turing-award/

As Professor of Computer Science at the University of California, Berkeley, Patterson led the Berkeley RISC project and now is an active member of the RISC-V Foundation, which offers a free and open ISA with the aim of enabling a new era of processor innovation through open standard collaboration.

You should spend five minutes Googling David Paterson, because you have no clue what you're talking about. Patterson's first RISC ISA project was called RISC-I. As in One. That was in the 80's. RISC-V is the fifth iteration of his work in that domain.

[MacroRodent]

Re: Sorry, what was the problem again?

From a legal standpoint all this is completely irrelevant, unless Patterson etc own enforceable patents in the RISC-V technology. (I don't know if this is the case). I doubt it. Instruction sets like RISC-V are old hat now, largely thanks to Patterson's work. He wrote a seminal text book on the subject, which I read decades ago and almost understood.

[CRConrad]

Please stop arguing like such a moron.

> Where does this notion of collective right to appropriating someone else's accomplishments come from?

Oh, I dunno... That's just how the world works? That's why patents, and even copyright (so far, knock on wood...) still do expire sooner or later.

Otherwise, you know, you wouldn't be allowed to express yourself here, in writing: The art of writing was invented by the Sumerians or the Egyptians or somebody, so Americans aren't allowed to do it. Or the wheel, also Sumerians or Chinese or whatever; so close all those car and truck factories, scrap or export all the cars and trucks, and go back to doing your land transport the American way: https://en.wikipedia.org/wiki/Travois

> Individual accomplishments are never democratized.

Oh, good. So then that accomplishment was Mr Patterson's, not "America's", to begin with, and since you claim that means it still is and always will be, you've just admitted that you haven't got a leg to stand on "as an American".

Sheesh. Can't you even see how stupid you're being? No? Well, that just confirms it.

[Slovrtux]

Re: Sorry, what was the problem again?

When Linus created linux he was student in Finland, part of is scholarship was paid by Finland .... Before you start thinking about ownership and how institutions can get a return on their investment .. take this 15 seconds you allow me to think what will be the other way to go, meaning patents and closed technology ... How it goes so well by sun and their sparc processor.

Reality is, if RISC-V will be closed platform, it will die like all the MIPS, Alpha and other plateform. Risc-v exist only because people's, who are not paid by ANY gouvernments spend times pushing and improving this tech.

And you definitely don't understand what open source and tech is about.

[Anonymous Coward]

Re: Sorry, what was the problem again?

> And you definitely don't understand what open source and tech is about.

Yeah. That's why Linus Torvalds retains the Trademark for Linux:

https://www.linuxfoundation.org/the-linux-mark/

Wherein it is clearly stated that the word Linux can only be used by a sub-licensee of said Trademark.

The Free Software Foundation retains the Copyright to the Linux source code.

Your assignment for today: write on the board the sentence "Open Source Does Not Mean I Own It" 100 times.

[CRConrad]

Re: "why Linus Torvalds retains the Trademark for Linux"

Yeah, that's probably why Samsung calls their ARM processors "Exynos" for trading, etc, etc.

Forthcoming RISC-V implementations will probably also be sold under varios more or less imaginative trade names.

So, let's get back to you when this argument becomes relevant. Pro tip: Don't hold your breath waiting.

[Justthefacts]

Re: Sorry, what was the problem again?

This is a strange argument, if I understand you correctly.

You are claiming that previous competing platforms died *because* they were closed? The mechanism was they lacked critical mass, which you say fundamentally comes from people “outside the ranch”? Your claim is that a fraction of the world equals lot of people willing to “have a go” because they are interested, is more productive than one large company who is paid and skilled to do the job?

There are reasons why open source *software* can work. The problem with your argument is that it applies to *everything* that is designed, not just computer stuff. Cars, for example. Open-source cars not just exist, but have done so right from the beginning. Kit cars and modified cars exist, and those who build them swap design ideas with other modders or kitters on forums. Some of them are experienced engineers, and produce frighteningly capable cars on very restricted budgets. And just for added spice, the electrical control interconnect on all cars is CAN bus, which was originally Bosch but absolutely now is awash with open source.

So, given that Open Source Cars do actually exist….why don’t most people own one? Why arent most cars standard like Linux, where a bunch of enthusiasts have designed a really good engine, + parts list. I *guarantee* you that if you start the Open Source Car Initiative, you will have ten *working* designs of 500hp engines in your inbox by tomorrow morning. And the job of car companies is simply to assemble The Open Source Car (variant#1639 customer option) to minimum cost? Until you can explain why cars and software world work differently, you can’t really understand whether open source is likely to be successful in the world of silicon hardware. And more precisely, which bits of it.

[steelpillow]

Re: Sorry, what was the problem again?

As the OP let me restate a couple of points:

1. Where or when RISC V was invented is irrelevant to the issues surrounding Open Source.

2. It's not the US government per se which is an unrelated problem, its nationalist governments - like China, Russia, North Korea, and yes the US too.

[Yet Another Anonymous coward]

Re: Sorry, what was the problem again?

Because things like OFAC and EAR controls are going to run up against opensource. If you are in the USA can you accept a pull request on your project from someone in Cuba or Syria or Iran?

Do you have to refuse to supply them with a copy of the source? If that's so are you able to comply with the GPL? Is the GPL invalid in any country that has export controls on opensource software?

It's a lot easier to scare politicians with stories about designs for "chips used in missiles" being given to foreigners than it is to talk about software licenses. If Intel somebody acting purely out of patriotism, gets a case made that you can't collaborate on an opensource chip design with foreigners. Then the same rulings are applied to software.

[Tams]

Re: Sorry, what was the problem again?

The CCP are a menace at best, evil at worst. We need ways to hinder them. I'm sorry, but if you can't see how they and Russia as they are making the world a worse place, they you're not the sharpest tool.

But doing so with instruction sets just seems like a waste of time and energy. x86, Arm, MIPS, RISC-V, they all get the job done. Shrug.

[Justthefacts]

Re: Sorry, what was the problem again?

International geopolitics doesn’t raise any problems at all that are specific to open-sourcing instruction sets.

However, a lot of commenters seem to feel that open-sourcing will *solve* some geopolitical supply issues. And they are simply wrong about that. It makes zero difference, because there are dozens of technical pinchpoints, precisely none of which is the instruction set. But because most of the people here are software people, not ASIC designers, they don’t know about any of the other pinchpoints, so this looks like magic beans to them.

Other pinchpoints: Necessary IP cores that aren’t the CPU; EDA tool sets. Have all the source code you like, but have you understood that what you might call a compiler, and we call synthesis, layout, design rule checkers, EM solvers, they are all under license, largely from companies like Synopsys headquartered in Mountain View? And yes there are some open source synthesis engines, but they’re *grim* - they work, but you’ll be paying a silicon area and clock frequency tax of 20-30%….if they don’t just crash under the load of any design larger than a hobbyist one. And then there’s packaging. Advanced packaging solutions like chiplets….who is doing that for you?

And I’ve really not even started on the problems of trying be independent of the US and China. Instruction-set….mate, if that were all it were, I would have knocked it up over lockdown on my laptop at home. It’s really not that hard. You just think it is, because it’s the only bit you come into contact with.

I know you think I’m being rude, but I’m really not. Look at it this way: the instruction set is the API to the hardware. If you had to code up Linux, *all of it* from scratch, and someone came up to you and said “psssst….don’t worry I’ve done it for you. Here’s the APIs.” How impressed would you be?

There’s no doubt they’ve done *some* work - structuring the problem is a big thing. But *all* of it - or even enough to make a big dent in coding the whole thing? No

[Tom 7]

Re: Sorry, what was the problem again?

There are open source tools for the whole of pretty much any ASIC design chain. There has been since I was designing chips in the 80s. Last time I looked I could feed the Verilog or VHDL into Electric or even Kicad and get a not particularly windy layout.

[Justthefacts]

Re: Sorry, what was the problem again?

Short version:

Fine for the 80s, not optimal, not suitable for what we need to do today.

Needs to incorporate - design rules that now number 10,000+, gate delay data from the fab which is under NDA and intrinsically not open-sourcable, power-aware design also involves feedback from test-vectors.

[Tom 7]

Re: Sorry, what was the problem again?

You get that data from the people you want to make the silicon though. It doesnt need to be open source but even the most stupid manufacturer would let you have it if you were paying them to manufacture it.

[Justthefacts]

Re: Sorry, what was the problem again?

You have the data….but not the tool chain it is going to plug into. I’m sorry to be direct, but you don’t know what you don’t know, and you are underestimating the size of the problem and “the set of things that needs doing” by not just one order of magnitude, but closer to three orders of magnitude.

I think the problem is that you are confusing two entirely different cases, as is everybody.

Case #1: A simple microcontroller class CPU. These are maybe 15-50kgate and the sort of CPU that people are saying “open source tools exist, hey we were doing this in the 80s, what’s the problem”.

Yes, that’s fine, you *can* do it. The problem is that the market is awash with solutions to that from a dozen different vendors and CPU instruction sets if you really want. There’s just *no need for another*. It’s already *done*.

Case #2: a general purpose compute engine of the sort that can run Linux, and be competitive in the modern and future world. Almost certainly superscalar, out-of-order, branch prediction etc.

The problem is that to one of *these* you will want to be on a leading edge technology - where for example the naive metrics of just counting NAND gates tells you little or nothing. And where most of the effort goes into power-aware design. And where there are just tons and tons of other large tasks including formal verification, and how you are going to manage ECOs etc.

The link below is a professional toolset of “what it actually takes”. Have a click through and see what the things are that need doing. And that’s maybe half of it, there’s plenty more in other tools. This is a toolset costing maybe $100k licensing cost *annually per seat*. This is normal in the industry. No, it is *not* replaceable by an open source tool written in the 80s, or Spice.

https://www.synopsys.com/implementation-and-signoff/fusion-design-platform.html

[Bruce Hoult]

Re: Sorry, what was the problem again?

You apparently aren't aware that the Berkeley RISC-V effort open-sourced in 2015 included not only the ISA itself but also a competent traditional 5-stage pipeline processor design, "Rocket", complete with good MMU, branch prediction, L1 cache, and FPU.

The design was picked up wholesale in commercial productions such as the SiFive FE310 (which competes well with ARM Cortex M3 and M4) and FU540 (which is close to ARM Cortex A53, despite being only single-issue). It is also used directly in the Kendryte K210, and influenced many others. The FPU design is probably used in a lot more -- fully IEEE 2008 compliant, and with full-speed handling of denorms (which is pretty unusual)

Rocket and its components has since formed the basis for dual-issue in-order and wider out-of-order CPU cores.

Assuming for the moment it's true that open source systhesis and layout pays a 20-30% area and clock penalty -- which I"m not convinced is true of yosys/nextpnr -- that's a MINOR price to pay for having an open source system. Especially when RISC-V cores are consistently 1/3 to 1/2 the size and 1/3 the energy use of otherwise comparable ARM cores.

The instruction set is a very big technical pinch-point because the entire software stack depends on it, and porting all the world's useful important software to a new ISA is a far bigger and more expensive and longer task than designing an SoC.

[Justthefacts]

Re: Sorry, what was the problem again?

Competent. Good. That’s a small fraction of the total work to release a competitive chip.

5-stage pipeline? Sounds like a design trade-off to me. What went into choosing 5? It will depend on a *very* complex interplay between the gate area of speculative execution, branch predictors, gate delays, and the power consumption of all of these things. These things change when you go from TSMC to Samsung, or 45nm to 28nm, let alone 5nm. Freezing that choice in 2015, and hoping it will be optimal in 2024 will *function*. But it’s not going to be a commercially useful chip.

If this were not the case, any company could take a chip it originally designed for 28nm, and re-target it to 7nm just by re-running it through synthesis and P&R. And, they still *can*, but nobody *does*. Instead it costs maybe $50m for a *very simple* chip, and maybe $300m for a high-end CPU, just to take what you regard as “the same source code”. They aren’t drinking pina coladas, they are taking a root-and-branch re-think of *every significant design choice*. Every damn process shrink, every time. Because if they don’t, the output is maybe 20% worse than their competitor in performance or gate area cost. You know how many they would sell in most cases? Zero.

That’s the point we disagree on. “The price for having an open source system”…..I assure you that price prepared to pay for any customer other than a government or NGO is precisely zero.

RISCV cores are *not* smaller and less power hungry than an equivalent ARM. It’s the opposite. You’re just wrong about that. Your statement doesn’t even make sense: on which technology? There are ARMs on 5nm. There aren’t any RISCVs.

“Porting all the worlds useful important software…..”

That’s either a very narrow, and wrong, statement, or it implies the opposite of what you think it does.

If by “software” you mean “the sort of stuff that runs on a consumer or enterprise general purpose chip”, then I give you the example of Rosetta. When Apple needed to change from x86, they just added a hardware translation layer.

If by “software” you mean “the vast majority of the worlds CPU cores, which are embedded and don’t run *any* operating system, let alone Linux”….well no, you are quite right. There’s no way I am going to take a motor-controller loop running quite happily on an 8-bit microcontroller and pay someone to port it to a RISCV just because it’s open-source.

Si5 FE310 competitive?

Well I simply googled “sifive Fe310 price”. Like you would. Hit #5

https://www.eevblog.com/forum/microcontrollers/is-the-sifive-fe310-a-toy/

“The entire user manual is only 116 pages long. This is ridiculous! How does SiFive expect to play in the professional MCU market with piss-poor documentation like this? It reminds me of the crappy documentation that comes with a lot of open source software.”

“Yes, it is a toy. It is a test chip that they decided to sell for fun. Also yes, FE310 is not a player in this market. You can't even buy them in quantity.”

“Hundreds of millions of SiFive cores will ship in 2020 inside Samsung's flagship phones (controlling the camera and 5G” [errrr, well, no they didnt. Samsung did their traditional beauty contest, and from my ears SiFive didn’t even make it into the last three. Sure, Samsung are “working with them”, they work with everyone, but there comes a moment when they dump you]

[Justthefacts]

Re: Sorry, what was the problem again?

Ok, now I’m starting to suspect that I’m the victim of a spoof.

That Sifive FE310 that you told me was “competitive” is according to the manual fabricated on TSMC 180nm. Yes, the decimal point is in the right place. I don’t know what to say.

Except that the derision of the buyer of that board when he read the user manual was fully merited. I think he underplayed it actually. This doesn’t even look like an early-access customer version, more like the sort of thing we would have punted around internally between groups - and still got howls of protest about “how do you expect us to work with this”

The electrical specifications are “ These electrical specifications are TYPICAL ONLY, and are not thoroughly tested in engineering sample parts. Production versions of the devices will be provided with a complete elec- trical specificatio”.

You will be surprised to know that there never has been an update of this to production version…..since 2017.

Not necessarily a problem in early dev….until you realise that in detail the info isn’t sufficient to define either a stable power supply or clock. The dev board is held together with string, to put it politely.

[4whatitsworth]

The important question

No-one is asking the important question here.

Is it RISC-Vee

or

RISC-5

What are we saying?

[Rudy]

Re: The important question

According to the spec (linked in the article), it is RISC 5.

[Yet Another Anonymous coward]

Re: The important question

The French have suggested a compromise, RISC-cinq

[Arthur the cat]

Re: The important question

For classicists it's RISC quinque.

[steelpillow]

Re: The important question

ρισκ πεντε, σιρλι (risc pente, shirley)

[Anonymous Coward]

Re: The important question

I've always thought Vee. With my track record, that almost certainly means it should be Five.

[Yet Another Anonymous coward]

Re: The important question

But pronounced JIF

[Anonymous Coward]

Re: But pronounced JIF

That was a lemon.

[Tams]

Re: But pronounced JIF

party

[Anonymous Coward]

This article is so confused and ill-informed it's almost funny

> On the one hand, it's all positive on the RISC-V front, with its open-source ethos [ ... ]

> On the other hand, the borderless nature of the emerging instruction set architecture – which is royalty-free to implement – could open another front in the chip arms race between the nations. Countries are turning to RISC-V to create homegrown processors and accelerators amid sanctions, shortages, and other barriers obstructing the free trade of semiconductor technology.

First of all, I did not know that there was a chips arms race between the nations. Which nations?

The author appears to believe that only the US, China and Russia design and make semiconductor chips, and that the rest of the world is completely left out of the chips party.

Is the author aware that countries such as the UK, Germany, France, etc, do have high definition TV's, microwaves, dishwashers, cars, smartphones, etc?

I've got news: there are many other countries that design and manufacture chips, besides the US, China and Russia. Does the author know, for example, that the UK, France, Germany, The Netherlands, Italy, Israel, Canada, Finland, Norway, Switzerland, all these countries are perfectly capable, and indeed do design and produce semiconductor chips?

Is the author aware that the major US chip manufacturers - Intel, AMD, IBM - have research centers in countries over the world?

> The US is threatening to cut off microchip supplies to Russia if the country invades Ukraine. But Russian companies that include Yadro and Elbrus are developing capable RISC-V cores as an alternative to x86 and Arm-based parts.

I don't know if this statement is intentionally half-true, or just ignorant. Yes, the US has threatened to cut off microchip supplies to Russia. What the author forgot to mention is that the US also depends on raw materials imported from Russia for its own production of microchips:

https://www.reuters.com/technology/white-house-tells-chip-industry-brace-russian-supply-disruptions-2022-02-11/

So does the EU, for that matter. Do the math.

> The Chinese Academy of Sciences, which is on the US Entity List of trade-restricted organizations, has developed 64-bit RISC-V cores while drawing on open-source blueprints made available by companies in America and Europe.

Correction:

> The Chinese Academy of Sciences, which is on the US Entity List of trade-restricted organizations, has developed 64-bit RISC-V cores copied from open-source blueprints made available by companies in America and Europe.

So, on the one hand, the US and the EU are making these microchip blueprints available to anyone to use, for free, and with no royalties. But then, and at the same time, the US and EU are persecuting Poor Little China. Awesome logic there.

Do the Chinese companies that manufacture these RISC-V chips record a profit from their sales of said chips? Chips that are based on designs originating in the US and the EU?

> But questions remain on which RISC-V chip developers, and in what countries, will be able to access Intel’s factories to produce components.

Not China and not Russia. Do China or Russia share their fab plants with the US?

> RISC-V is appealing because engineers have the freedom to implement the specification, optimizing and extending their designs as they need, or use an off-the-shelf core, and the modular nature of the architecture's extension system to meet different workloads in computing.

Aha. But the US - BAD. We gave you the RISC-V ISA for free, we published silicon designs on GitHub, but hey, Intel isn't willing to share with China their fab production lines that are designated National Security, because these have military applications. And because we don't really want Chinese spies running around and copying PDF's more than they already do.

What's next? Should Intel also fab China's chips for free, so that they don't feel so persecuted and left out?

If you want to make chips, build your own fab plants.

[John Brown (no body)]

Re: This article is so confused and ill-informed it's almost funny

"We gave you the RISC-V ISA for free, we published silicon designs on GitHub,"

And no one, anywhere has done anything to develop it from the basic teaching demonstration. If your "we" want to claim "ownership" then your "we" should not have released it as "open". Where would the USA be today if "they" hadn't copied actual patented inventions, ignoring the patents? Ask Charles Dickens what he thought of US copyrights before they joined the civilised world.

[Anonymous Coward]

Re: This article is so confused and ill-informed it's almost funny

> [ ... ] your "we" should not have released it as "open".

I don't quite follow the logic here.

We gave you the ISA Spec for free, no royalties, and we gave you Verilog and VHDL designs for RISC-V silicon, for free, with no royalties.

You probably don't know this: open sourcing an ISA requires NSA export control approval. They could have easily said No and that would have been the end of royalty-free and open RISC-V.

"Open" doesn't mean it's yours, or that you invented it.

Someone made chips out of these designs that they got designs for, for free? Great! Bake your chips, sell them, make a profit and STFU with this endless litany of complaints.

If it weren't for the designs that they got for free from us, there wouldn't be a chip to sell, and there wouldn't be any profits.

There is nothing more obnoxious than a non-American who hates America, but wants to imitate it, fails at it, and then resents us for their own failure. And that in spite of America's numerous and major defects.

[martinusher]

Re: This article is so confused and ill-informed it's almost funny

>If it weren't for the designs that they got for free from us, there wouldn't be a chip to sell, and there wouldn't be any profits.

Of course there would. The RISC-V type of architecture is used in numerous processor designs. But they all have slightly different instruction sets. The key thing is standards.

>There is nothing more obnoxious than a non-American who hates America, but wants to imitate it, fails at it, and then resents us for their own failure. And that in spite of America's numerous and major defects.

I am an American and I'm very familiar with the "Love it or Leave it" mindset, a mindset that's now reduced to a rather pathetic "MAGA" (or "Save America" which we're due to be bombarded with 'real soon'). America -- and Americans -- need a bit of 'tough love', not mindless patriotism. We screwed up by putting profits above all, exploiting cheap labor around the world and neglecting our own people, adopting the attitude that we don't need to compete because We're Number One. Unfortunately, the rest of the world begs to differ and in China we've finally come up against an economy that can look us eye to eye as equals. It hurts but throwing tantrums isn't going to fix things, its just going to make matters worse.

[Anonymous Coward]

Re: This article is so confused and ill-informed it's almost funny

> America -- and Americans -- need a bit of 'tough love', not mindless patriotism.

First off: Keep your MAGA speculations to yourself. You know nothing about my political affiliations.

Second: you seem to believe that there's no-one more qualified to administer this 'tough love' to America than some random collection of Internet boobs who have no clue what they're talking about and can't even regurgitate simple facts that can be found and verified with a simple search.

> [ ... ] in China we've finally come up against an economy that can look us eye to eye as equals [ ... ]

Keep telling yourself that, if that's what you want to believe.

China's economy is based on cheap labor for advanced economies. It's a glorified assembly line for products designed elsewhere.

And this economic miracle that you're so in awe of is not structural. Most of China still lives at the subsistence level. There is a very thin layer of relative prosperity that covers a very small number of people relative to their population.

The moment we decide to pack up, leave, and close our markets to them, their economy is toast. They can sell their products to Vietnam and Venezuela. Unfortunately, that's not where the money is.

And they know it themselves. Xi is looking for a new friend, as in Putin. And he's threatening to attack and annex Taiwan because he knows full well that China can't compete on its own with an island that's 267 times smaller. That should tell you everything you need to know about China's real economic potential.

[werdsmith]

Re: This article is so confused and ill-informed it's almost funny

Argumentative chap this ST, seems a bit triggered.

Needs to sit down and relax with some beer, but not that piss stuff that needs to be chilled so you can't taste how bad it is. ;)

[CRConrad]

Re: Argumentative chap this ST, seems a bit triggered.

Claims not to be a MAGA-hat, but if so, obviously belongs to some other very similar and just as stupid variety.

[CRConrad]

This commenter "ST" is so confused and ill-informed it's almost funny

> > [ ... ] your "we" should not have released it as "open".

> I don't quite follow the logic here.

Probably because you, oh-so-conveniently for your crooked argumentation, left out the first half of the sentence. (That couldn't by any means have been intentional, now could it?) Here, to remind you:

> > If your "we" want to claim "ownership" then your "we" should not have released it as "open".

And here, the crux, the central point you seem to be yammering about:

> "Open" doesn't mean it's yours, or that you invented it.

So f--king what?!? Is anyone claiming it's "theirs", or that they "invented it"? (Besides you, that is, who by virtue of being American are apparently an avatar of mr D. Patterson.)

No, nobody (else) is claiming that. So stop fucking gibbering about something that isn't happening.

[Yet Another Anonymous coward]

Genuine question RISC-V / ARM

As somebody who assumes that the "adding lightning to sand and making it think" is basically magic and who just does software.

RISC-V just defines an API right ? Presumably there aren't too many innovative new Assembly Language instructions, especially in RISC, they are supposed to be simple right? (This is based on my doing a few weeks of ARM2 assembler after having learned 6502 as a kid)

So what's the massive lead of ARM over RISC-V? Obviously the silicon design of an Apple M1 is incredible, but you get this by being Apple+TSMC, not by buying an ARM license. Presumably Apple could have done the same design around a RISC-V instruction set?

Does ARM supply all the super-scaler / out of order pipeline / branch prediction magic we all rely on - as part of the licence design? Or is it just that there are more optomised ARM core designs out there, more people familiar with them, more tooling, more compilers etc etc ?

[Tom 7]

Re: Genuine question RISC-V / ARM

RISC-V defines the API but there are also many freely available Verilog or VHDL or other languages complete CPU designs that you can take and either process straight into silicon CPUs layouts (or even GaAs) with open source tools if you have a process to target, or modify and extend for your own purposes. The open bits and pieces libraries seem to grow weekly and there's even GPU stuff that you can play with and evaluate and extend.

[Justthefacts]

Re: Genuine question RISC-V / ARM

Yes.

Why?

I think you said it: to play, evaluate, extend.

C’est gloire. Mais ce n’est pas la guerre

[Justthefacts]

Re: Genuine question RISC-V / ARM

The difference is mostly ARM implementation.

Yes, all the superscalar, branch prediction etc, will be part of the IP core that ARM are selling to most people, plus dozens more things under the hood that will save a % here, a % there.

For most companies, if you simply download a RISCV and send it to TSMC 5nm…..who is going to tell you that it would be 3% more optimal to have used 2pA drivers on the data bus, because although it sinks more power instantaneously it allows the cache to doze earlier in 90% of cases, and that your experience on TSMC 7nm is giving you the wrong steer. ARM will have already done the job before for fifteen other companies, on the technology you haven’t used yet. Why would you either reinvent the wheel, or rely on your competitors to do your job for you.

Apple is a different case. They *do* have the expertise (or can pay for it). They bought an ARM license, not an ARM core. Very few companies do. The only other one I can guess might be Qualcomm, I just can’t think who else. Even companies like TI are just buying the core outright. Could Apple go to RISCV? Probably. I just don’t why they would bear the upset and tools transition to do it.

[DS999]

Re: Genuine question RISC-V / ARM

Apple wouldn't benefit at all from switching to RISC-V or creating its own ISA. The fees they pay to ARM for their architectural license are rather modest, it would take many years to recoup what it would cost them to go to a "free" ISA - probably many decades to recoup if they developed their own.

Even though they don't use ARM designed cores they still derive some benefit from using the ARM ISA for their own cores in terms of improvements made to LLVM (the base of their compiler) for ARM, and maybe someday from Windows/ARM if that ever becomes widely used and people want to run Windows/ARM in a VM to access certain applications not native on macOS.

Plus they still have flexibility in adding their own non-standard instructions if they want, their only real limitation is that their ARM chips must be able to pass ARM's certification tests so they can't change the meaning of existing ARM instructions. Once they were able to drop support for AArch32 and go 64 bit only they shed any legacy debt so have a pretty clean ISA that doesn't require supporting stuff they don't use or care about in 2022 like x86 designs must. That may be a minimal cost for Intel and AMD since those older 16 bit modes etc. don't change, but it isn't zero.

[bazza]

Re: Genuine question RISC-V / ARM

Maybe Samsung have a license too?

[Justthefacts]

Re: Genuine question RISC-V / ARM

Yes, I think so, Exynos is ARM.In fact I suspect I *know* so, from internal knowledge, but Samsung is a very odd company, so it’s difficult to be sure.

The issue is that it is the reddest in tooth and claw in the world. They usually have two or even three different sites of Samsung working completely independently and competitively against each other to produce the same output. And then at the end, senior management swoop in, and do a beauty contest between those three designs and at least one shortlisted external. There is *no* preference for an internal candidate, it’s technicals and cost only. And all the losing internal teams are simply fired, or at best asked if they want to reapply for a job with a different team on a different project. Samsung are *brutal*.

But the consequence is, anything you think you know about what “Samsung” are doing, is simply wrong. All you ever know is what one internal bidder is doing.

[DS999]

Re: Genuine question RISC-V / ARM

Samsung does, but they gave up designing their own cores a couple years ago after failing to match, let alone beat, standard ARM cores in power and performance.

[Tom 7]

Re: Genuine question RISC-V / ARM

TMSC would tell you all the details you need before you send them the chip to build. Its not in their interests to waste your time giving a bum steer.

[Justthefacts]

Re: Genuine question RISC-V / ARM

Rubbish. What I suspect is that you are failing to differentiate between two different types of RISCV CPU.

If what you are talking about is a “Linux class” CPU (Superscalar, out-of-order, branch-prediction, probably multi core, probably with cache coherence circuitry).

Doing the *actual work* of understanding what makes a difference and why, is different for every chip, and easily costs you $200m per new chip on leading edge. There’s no way TSMC are going to do that for you for free, and they don’t even have the expertise. Make tradeoffs of driver-strengths and clock speeds, and dozy caches etc, etc, just isn’t “what they do”. That isn’t their market niche. There is a company who very specifically that *is* what they do. It’s what they spend most of their manpower doing, and they are good at it. ARM.

It’s certainly *possible* to be better. But you definitely need to be in that Tier #0 of companies with the expertise. You and your little ‘ole Unicorn Startup with $100m in VC cash….you’ve got *no* chance of being as good. Zero.

[Bruce Hoult]

Re: Genuine question RISC-V / ARM

RISC-V just defines an API right ? Presumably there aren't too many innovative new Assembly Language instructions, especially in RISC, they are supposed to be simple right? (This is based on my doing a few weeks of ARM2 assembler after having learned 6502 as a kid)

Right.

There is deliberately nothing innovative in the base RISC-V instruction set. It set out to learn lessons from 30 years experience with RISC and use the best parts from RISC-I and -II, SPARC, MIPS, ARM, POWER, Alpha and others. Not from Aarch64, which was developed largely in parallel, with the basic RISC-V design being already in place when the Aarch64 ISA was published in late 2012. They *both* took many of the same lessons from experience, though Aarch64 is a bit constrained by having to run (at least up until very recent designs) on the same CPU pipeline as Aarch32, and also ARM don't seem to intend it to ever be used in the smallest devices.

The most innovative part of RISC-V so far is the just ratified Vector extension. Again, it's similar in a lot of ways to ARM's SVE. They may have both had the same influences, though it seems quite likely that SVE was influenced by the Berkeley research into vector processing. RISC-V was actually initially wanted as the scalar control processor for vector processors already in development.

So what's the massive lead of ARM over RISC-V? Obviously the silicon design of an Apple M1 is incredible, but you get this by being Apple+TSMC, not by buying an ARM license. Presumably Apple could have done the same design around a RISC-V instruction set?

Indeed Apple could have. RISC-V didn't yet have all the standardised ISA parts Apple needed at the time they started development of the M1 -- and of course not back when they made their first Aarch64 chip for the iPhone 5s released back in 2013 (and 1.5 years before ARM and their partners had 64 bit CPUs ready for the Android market e.g. Samsung Galaxy S6).

Apple wanted to get Macs on to the same ISA as iPhones and iPads, and for the moment that meant Aarch64.

Personally I think that within five years Apple will switch *everything* to an ISA they have greater control over. I don't know whether that would be RISC-V or something they design themselves.

The lead of ARM over RISC-V is mostly that they started earlier. In the case of the M1, Apple has a lot more money to spend than ARM does.

Currently shipping RISC-V cores that you can buy on an SBC (e.g. SiFive HIFive Unmatched, Starfive VisionFive v1, T-Head ICE RVB) are about 5-6 years behind ARM (e.g. Pi 3).

If you are starting to design a chip today then the RISC-V cores you can license for it e.g. SiFive P650 are about three years behind comparable ARM designs (Cortex A76).

Does ARM supply all the super-scaler / out of order pipeline / branch prediction magic we all rely on - as part of the licence design? Or is it just that there are more optomised ARM core designs out there, more people familiar with them, more tooling, more compilers etc etc ?

ARM supplies the pipeline and branch prediction if you license one of their cores. They don't if you simply license the ISA and implement your own core, as Apple does.

There is no significant difference today between the quality of gcc or LLVM compilers for ARM and RISC-V.

[Justthefacts]

Re: Genuine question RISC-V / ARM

I agree with every word, other than “three years behind”. I think it’s 8 years behind.

The issue isn’t the features, it’s the readiness to target the fab process, and the experience of the fab with that core and process.

If you were to do a design start today with TSMC leading-edge, ARM would hand you a core that has *already been verified* in N3 risk production. Not just that, you do it in the sure and safe knowledge that if you do hit yield problems you are standing with every lead manufacturer on the planet. TSMC are going to solve your yield problem if they die trying, and they have literally $40bn standing ready to solve their customers problems. It’s what they do.

If you go with RISCV, the best anyone can tell you is “something quite like this worked a couple of generations ago”. There’s just no way your chip is going to work on the first spin, to any level of working. It’s not a RISCV thing, it’s a “new design on a new technology” thing. And just so Software people understand, it’s not the “source” code as you understand it. It’s stuff like clock-trees, and power domains, and power-droop in the middle of the wafer, and clock-crossing edge-cases where it interfaces with the cache, which is a bought-in memory IP from a different vendor. And your *second* spin might work but is almost certainly going to be beset by yield problems too, to the point where you aren’t going to be able to ship in volume economically. Sifive have exactly this problem: even the products they originally taped out in *2017* still don’t have fully production silicon available. So there are plenty of enthusiastic hobbyists who received dev boards….but that’s as far as this goes.

So I think when you include needing to go to third spin of the ASIC for production volume, when your competitors are shipping right-first-time silicon, it’s eight years behind.

[Tom 7]

Re: Genuine question RISC-V / ARM

I was running Spice simulations on 10,000 device chips with data extracted from the actual in the lat 80s. Something like RISC-V could be spiced up and simulated well enough for it to work on silicon first time with relative ease on a laptop these days.

[Tom 7]

Re: Genuine question RISC-V / ARM

Sorry Spice data extracted from the actual layout - so all the parasitics and power line resistance and capacitance all there for power line droops and resonances.

[Justthefacts]

Re: Genuine question RISC-V / ARM

Moving goalposts and whatabouttery…..

Look, what type of market niche are you looking to fill with this RISCV? It’s a very basic question.

If all you want is to design a cheap microcontroller, then you can etch it by hand with kindergarten crayons. The problem is that the market has had a dozen competitive ones from different companies, for two decades, and really there’s no room for yet another. Nobody needs to do this again *ever*. It’s. Done. Please. Stop.

But if you have in mind some high-end superscalar out-of-order more general purpose computing engine…..the teams you want integrate it are using professional high-end toolsets, not a bunch of crayons. And if you have you have *any concern at all* that your Design Team would lose access to a “core controlled by the USA”, they lose access to their copy of (for example) Synopsys Fusion Compiler at the same instant.

Spice just isn’t in the same universe for “the set of things that need doing”.

https://www.synopsys.com/implementation-and-signoff/fusion-design-platform.html

[steelpillow]

Re: Genuine question RISC-V / ARM

While a core RISC instruction set is inherently simple, there are several different ways that implementations can differ.

Firstly, the precise binary word to define say "add the contents of register 1 to that of register 2 and put the result in register 3" may differ, much as grammatically similar human languages do.

Secondly, designers' ideas on "how reduced is reduced" naturally differ in detail. Sometimes there can be two different ways of cutting things down which are logically equivalent but have implications for the silicon, a bit like broadly similar human languages swapping the word order around.

Secondly, there are a great many things that one wants to put in an API, which the silicon may not be able to do. For example early ARM chips had no multiply function, that had to be done as a library routine. Soon the function was supplied by an optional Arithmetic Logic Unit (ALU) chip with its own API. So multiplying was not a part of the RISC core API. Later ARM processors included the ALU on-chip, so the APIs had to merge into a single, not-so-R ISC. Then people started adding vector processing and multiple cores and all kinds of other stuff. All the while the APIs grew more complex (though still simpler than Intel's x86 set) and that led to them growing ever further apart, like say Greek and Danish growing apart from Proto-Indo-European.

Thus, there is no "One RISC to rule them all". ARM grew dominant because it was one of the few RISC offerings around and developed a flexible licensing model, where chip makers could incorporate it into their own products; unlike Intel, ARM does not have any waferfab. It turned out to be a great market niche.

[MrReynolds2U]

Re: Genuine question RISC-V / ARM

"adding lightning to sand and making it think"

you've made my day, so have a beer on me :)

[3arn0wl]

Ah the Nationalist's backlash to Intel making a wise decision to put some funding and design effort into an ISA which will make them competitive against Arm in embedded, microcontrollers, IoT, edge, SBCs, tablets and smartphones. That will help deliver Server2. But all the Nats will see is that it's taxpayers dollars funding stuff that enemies get the benefit of.

Well, a few things:

- RISC-V International is based in Switzerland... In 2019 the foundation took the astute decision to de-camp for this very reason. RISC-V is not American : it's International. The gods who put RISC-V together - standing on the shoulders of giants (not least of Turing) - are Internationals : Krste Asanović grew up in the UK...

- whilst RISC-V is an open instruction set, companies' RISC-V IP can be open source or not. Now, so far, Western Digital, CAS and Alibaba have open sourced designs, but companies like SiFive and Andes haven't, so far as I know.

- companies can develop their own extensions, and not share their advantage. There's nothing preventing anyone from producing kick-ass RISC-V chips that others can't compete with.

At it's purest, RISC-V was an academic paper about what is the best way to do computing, and looking ahead (at the time) to some of the issues being faced in chip design. The fact that it's turned out to be a good instruction set that companies want to use, is a testament to the academics.

[martinusher]

So that's the beauty of open source

The US really kicked this off years ago with their restrictions on the export of encryption technology. The result was that when it became time to develop new standards and algorithms the US was effectively shut out -- not people, obviously, but nothing originating in the US could be considered because of the bureaucratic stranglehold exerted by the government. The same goes now for any other important technology -- develop it the US at your peril.

All that RISC-V does is provide a global standard architecture with the promise of compatibility across manufacturers. Like other open source initiatives its not anyone can own or restrict, its just an agreed foundation that we all work from. Its not something a politician can control, restrict or own and their attempts to treat it as such are as pointless as trying to monopolize printing or book production.

[Justthefacts]

Re: So that's the beauty of open source

That’s just nonsense. Firstly, crypto has always been restricted, since WW2, you only found out about it when *you* started to care about email privacy in the 90s. But the largest set of computer standards anywhere are the IETF RFCs, obvs, and they were mostly originated in the US.

And since you clearly haven’t understood how the world really works…..how do you think the US would implement a restriction on the licensing and use of IP or standards developed there? Since it isn’t *made* in the US? What you’ve not understood is that all the US has to do, and *does* do, is use its economic muscle. It tells the exporter, like it or not,

#1 If you do this, we will never buy from you again.

#2 In the limit, we will disconnect you from the global SWIFT payments system. Then, you can’t get paid for anything, by any other country. It does this to Iran.

So pretending that somehow using “your own IP” is going to change the balance of power is delusional. The US Commerce Department will tell TSMC *exactly the same* whether you think it’s legal or not, if it is sufficiently important to them. Sometimes you just have to live in the real world.

I’ve had it done to my project, twenty years ago. We (U.K.) had a contract with a country in the Far East, for an advanced technology. The US made it clear they didn’t approve. We went ahead anyway (they can’t stop us, right?), made the chips (in a U.K. fab!), sent them off to be packaged in S Korea. On their return, mysteriously the chips went on a different ship than they were supposed to, which happened to go the other way round the world, and landed at San Francisco on the way, where they were confiscated by Customs for investigation. And that was the end of the project.

I’m sorry, sometimes you just have to live in the world, not how you would like it to be.

[Tom 7]

Re: So that's the beauty of open source

We designed an RSA chip to scramble speech and got a visit from some men in suits just before it went to silicon and it didnt.

[Justthefacts]

Re: So that's the beauty of open source

Of course, you understand the ultimate irony in this “global standard architecture”, right? At the low end, basically from 8-bit microcontroller up through 16-bit in-order CPUs, this is likely to become the ultimate commodity at a cost level you haven’t even considered.

The *real* innovations over the past few years have been in packaging, which is changing the whole landscape. Chiplets, or System in Package as we used to know it. The whole concept of “cores” is quite likely to disappear. Why would any chip manufacturer with some particular concept, want to take on the complexity (and risk) of integrating a very standard core on chip? All you do is stack your stuff in package with some else’s commodity chip. Let’s call it RISCV if you like, absolutely nobody cares.

If all this chip is, is 20kgates of nothingness that fits in *microns* rather than millimetres, which is just a clock, power, GPIO controller, then not only is this worth only 10 cents , 8 cents of that is the cost of the package and production testing. For chips of that size the area becomes almost irrelevant…..because there are a certain number of external pins that any chip has to have, which have a size, which fixes a minimum *perimeter*, which means there’s a minimum chip size. The chip cost is determined purely by the number of external pins. And *thats* why low end chips are made in 90nm+- anything smaller, and the silicon would basically just be some big blobs on the outside and tiny pimple of transistors surrounded by empty space. *Packaging* in QFP is everything, and once you remove that, all the economics change.

So in future, never mind whether Europe or USA or China are going to make these….they aren’t going to be *sold* by any *chip manufacturer* at all. They will be microscopic flakes embedded into every package that comes out of Kyocera, Amkor et al. It’s going to be part of the standard chip *pacakge*.The “value” of this is well under 1 cent per chip in that new world, perhaps as low as 0.1cents.

[Justthefacts]

Re: So that's the beauty of open source

I keep “itching” away at this, but I just don’t think people have *any* concept of the numbers we are really talking about here.

On 3nm, you get 170Mgate/mm2. A low-end 20kgate microcontroller (20kgate) would fit in a 24micronx24micron patch if you didn’t have to worry about the large contact pads, and could contact it with Through Silicon Visa instead, which is now fairly established technology. Within five years, the entire CPU fits *inside one 8 micron bonding wire”. This isn’t going to be something you sell, it’s going to come free with the package.

Value? On 3nm, 300mm wafer, just a single wafer fits 113million of those devices. On 2nm, it’s going to be 200million devices. Per wafer. If every individual in the EU bought a hundred devices a year…..it would be 200 wafers annually. That’s *six minutes worth* of TSMC production capability. This is not a big market by value, to put it mildly.

Yes, I know that’s not the situation today. Today these devices are compeitive because they are etched in children’s crayons due to the packaging limitations. But those limitations are going away. Non-technical commenters are making the classic mistake of focusing 5-10 years worth of investment to reach the point they see today, rather than thinking how it will be in 5-10 years time.

And that’s 3nm. In 10 years time, that’s going to be a legacy node.