2021: Remember when IBM use to make chips instead of patents backed by vague claims?
2031: Remember when Intel use to make chips instead of patents backed by vague claims?
Intel's really at a branchpoint here.
Samsung has added a 2nm process node to its foundry roadmap, and said products built with the new tech should go in sale in 2025. Whenever it lands, the chips will use the gate-all-around (GAA) technology the South Korean giant debuted in 2019. As The Register previously detailed, GAA is an attempt to pack more transistors …
The node names now are just a continuation of the node names from when they stopped using planar transistors. Because those were made differently from the transistors we use now, modern transistors no longer have a proper "gate length" dimension that used to be reported as the node size.
With planar transistors, the shrinking gate length very closely tracked increases in density - i.e. if the gate length was halved you got ~4x more transistors in the same area. So they initially continued with the same "X nm" numbering system to represent the continuing increase in density even though it was no longer measuring a physical length.
Since there was no longer a relationship to a physical property TSMC started referring to their processes with names like "16FF" and "N7" and so on years ago, then more recently Samsung did the same with names like 3GAE, and now Intel has finally joined them with their "Intel 7" "Intel 4" etc. naming they recently announced. But no matter how many times TSMC refers to "N5" as such, the tech press keeps reporting it as "5 nm". It doesn't help that the people writing press releases do the same, while the CEOs and engineers never mention nanometers.
Theoretically they could have chosen names based on number of transistors they can fit per mm^2 of size - with TSMC's N3 that figure is 292 million. But as there's no standard way to measure those densities (i.e. transistors doing WHAT per mm^2) and actual chips don't reach those densities for reasons unimportant to this point, it wouldn't necessarily be any better.
All we need to know is that "3 nm" is better than "5nm" and should have somewhere in the ballpark of double the transistor density - though in the drive to introduce a new generation every two years TSMC has been achieving density improvements in the 1.7x to 1.8x range lately and even less for Samsung so just consider it to be "more" transistors rather than twice as many.
Well instead they pretty much followed the foundry model of giving them names instead of numbers that represent real figures.
Why do you think Intel went to processor numbers instead of marketing on GHz? Because Pentium 4 had much higher clock rates than the Core line that followed, they knew that marketing on GHz would cause consumers they'd trained for 20 years to think clock rate is all that matters to believe these new CPUs were worse.
So now they sell an i7-10465G or some other meaningless number. Not really all that much different than N5P or 3GAE. Sure you can find out what the clock rate is (though there is base and multiple turbo states so even that isn't a single number anymore) along with the number of cores, etc. on Intel's Ark site, just like you can find out the physical dimensions and other relevant information of N5P transistors if you dig around.
A single silicon atom is about 0.2nm (two ångströms) in size, but you need more than one atom to produce a working gate, so we're already pretty close to the limit in that respect.
But even before you get that small the wavelength of light used in the etching process is problematic. I think newer processes are already using extreme ultraviolet light to etch the silicon because visible light was no longer viable. Beyond that you'll have to start using soft x-rays which I'm sure will bring a whole host of new problems to solve.
No we are nowhere close to that limit, because the transistors in a "2nm" process are much much larger than 2 nanometers in size.
In labs there are transistors that use single molecules, or sheets one atom wide that would be equivalent to another couple decades of improvement in density from where we are now.
It is far more likely that we reach economic limits well before we reach physical limits. At some point we may know how to make denser chips but building the equipment able to make them and a fab able to house it will cost so much that there aren't enough customers able to depreciate that massive investment. Even a company as rich as Apple with a massive quarter billion iPhone/iPad/Mac SoCs per year volume couldn't afford to go it alone if all TSMC's other customers fell away and refused to follow them to the next generation.