PCIe 6.0 spec just months away from completion, doubles max data transfer rate

A key standard set to double data transfer speeds between the main components of computers will be finalized in a matter of months. The final specification for PCI-Express 6.0 is targeted for the end of this year or early 2022, Al Yanes, president and chairperson of the standards organization PCI-Special Interest Group, told …

[bazza]

Dear Holy Cow

That's fast...

[Mike 137]

Fine, provided ...

I only hope that this has doesn't result (as usual) in the need to replace all our hardware to ensure expansion remains possible. Each time there's a new interface version, vendors stop making expansion parts for previous versions in short order. We keep systems running for as long as possible as that saves a fortune while they still work (and also in a small way reduces the WEEE mountain). But it's getting increasingly difficult to do so.

[ibmalone]

Re: Fine, provided ...

PCIe has typically been forwards and backwards compatible with other PCIe versions.

[Anonymous Coward]

Re: Fine, provided ...

Its the same interface, just faster (like all previous versions), older PCI Express cards work in it and new cards, if designed to do so, work in old slots, just at a slower speed.

[John Robson]

Re: Fine, provided ...

It explicitly says that in the article...

[genghis_uk]

Re: Fine, provided ...

Not quite - the speed stays at 32GT/s but the physical and data link layers are quite different in Gen 6. PAM-4 signalling, error correction, fixed packet sizes etc... However, the intent is to still interoperate with older systems.

We are only just seeing early samples of Gen 5 devices so that will not become mainstream until 2022. I can't see Gen 6 making a real impact for a few years - this cycle could be much longer than the 18-24 months we normally see

[katrinab]

Very nice, but I'm still on PCIe 3 and hope to take delivery of my first PCIe 4 machine before the end of the year.

[batfink]

Sorry for my ignorance but...

Why is the automotive sector excited about this? What goes on in a car that requires this kind of bandwidth?

[jason_derp]

Re: Sorry for my ignorance but...

You might be thinking of regular old cars. It's AI-assisted "self-driving"+ cars that care about bandwidth, I believe.

[bazza]

Re: Sorry for my ignorance but...

So they can arrive at the scene of the accident even quicker...

[Anonymous Coward]

Re: Sorry for my ignorance but...

Just how much bandwidth is required to find a police car and aim at it? They don't move that fast.

[hup hup hoo]

Not bandwidth

Probably not additional bandwidth per-se (though as mentioned plenty of in-car systems will eat it up), it's as likely due to the ability to use few lanes for a given purpose which reduced cabling/interface costs and may mean a chip with 16x lanes no longer needs a separate multiplex chip etc.

Just a guess.

[Anonymous Coward]

Re: Sorry for my ignorance but...

Radar systems use plenty of bandwidth. Same for vision processing. In both cases, the bandwidth will be within a module, not running from one end of the car to another. The heavy bandwidth will be between a sensor and the processing hardware. A vision module will typically crunch a bunch of data from its own camera and then tell other modules (over CAN) something like "hey, there's a pedestrian ahead and slightly to the right". The actual processed information is relatively short and low bandwidth (but still time critical).

On a well designed system, another sensor, maybe a radar, maybe LIDAR, also crunches its data. Ideally it says "hey, I see a pedestrian-sized target 8m ahead, moving at 1m/s from right to left".

Meanwhile, a central system hears both data points and warms the driver to be alert to a pedestrian about to cross the road.

Where module to module bandwidth is important, you'll see CAN-FD or automotive Ethernet (I haven't personally seen flexray, that's our there as well, although I think that was most often used in infotainment).

[Dazed and Confused]

Great but

Why are PCIe specifications only available to PCI-SIG members?

The nosy amongst us would love to be able to ready through all the output of lspci and be able to look up what it all means.

The likes of SMBIOS and UEFI are all open docs these days, why is PCI secret?

[bazza]

Re: Great but

This is pretty normal, and it's all about funding. It actually costs quite a lot of money to develop, maintain and improve standards, way more than the amount of money it costs to be a member of the SIG. Being a member gives you access to some very valuable intellectual property. It probably also involves you giving a commitment to not rip off the IPR (i.e. pay any royalties on relevant FRAND patents that are involved).

For software, even if there was a professional crew writing it or developing a standard for it, there's precious little more than manpower involved. Whereas hardware standards like PCIe, someone may well have spent several hundred million dollars on silicon design and fabrication, just to see if it actually works. So it's understandable if the body(ies) that developed it are a little bit reticent to just give all that away for completely free; FRAND royalties really count as a motivation to do the initial expensive work.

Besides, someone has got to manage the list of vendor and device IDs.