New release of SweRVolf RISC-V SoC project aims for lower barrier to entry

The SweRVolf project, a fully open system-on-chip designed as a reference platform for Western Digital's RISC-V SweRV cores, has announced a major new release promising lower barriers to entry for those looking to experiment. "Western Digital released the first of the SweRV cores, EH1, in 2018," Olof Kindgren, senior digital …

[Will Godfrey]

Looks interesting

I just wish I was ummm... about 30 years younger!