Deep neural networks... IN SPAAACE: Vector-enhanced RISC-V chips could give satellites onboard AI

Boffins from the Delft University of Technology (TU Delft) and European Space Agency (ESA) have penned a paper detailing the design of a processor they hope could run deep neural networks in space – building on the free and open-source RISC-V architecture and its vector extensions. "One of the main issues in terms of hardware …

[Anonymous Coward]

Speed vs. Size

As a concept it sounds interesting but, as the author points out, implementing it on current hardware would result in a device that's too big.

In space size always trumps speed. Until a chip manufacturer steps up to the plate with a new 28nm hardened chip design, it will remain just a concept. It will be years to design, build, and test the chip, more years to develop the physical device, and more years to design satellites to use it.

Still, I wish them well and offer the boffins a pint.

[Bruce Hoult]

Re: Speed vs. Size

Not really correct, as FPGAs typically have a lot of ALUs in them (referred to as “DSP blocks”) and using them to implement a vector processor makes perfect sense. You’ll usually only get 50-100 million instructions per second from a soft core in an FPGA, but if you have long vectors this doesn’t matter. The RISC-V vector extension lets the exact same code run on machines with vector registers of any length. There are rad-hard FPGAs available off the shelf.

I’d expect to see a scalable open source FPGA implementation of the RISC-V vector extension within the next 12 months.