RISC-V boffins lay out a plan for bringing the architecture to high-performance computing

RISC-V International, the nonprofit at the helm of the free and open CPU instruction set architecture, says it is writing a high-performance computing (HPC) roadmap of "new features and capabilities." For an architecture which only began life at the University of California, Berkeley, in 2010, RISC-V has enjoyed considerable …

[Elledan]

OpenRISC

So what advantages does any of this have over OpenRISC (open ISA & open reference design), OpenPOWER (open ISA, multiple reference designs based on older Power silicon) or OpenSPARC?

These glowing self-congratulatory pieces are getting somewhat tiresome, to be honest. Where's the journalism?

[diodesign]

Re: OpenRISC

The advantage of RISC-V over OpenRISC is that it has more momentum, more financial backing, more corporate and enthusiast interest, and (I'm pretty sure) more hardware available now or on the horizon. It's an Arm rival that seems to have gained traction.

OpenPOWER and OpenSPARC just seem out of reach. We do keep an eye out for them. I can imagine folks feel OP and OS are a little encumbered by their parents, IBM and Oracle, respectively.

Also, Intel just reportedly tried to buy a RISC-V startup for $2bn+. I don't see that happening with OR, OP, and OS outfits.

If there's a screw-up in the RISC-V world, then let us know if we don't spot it, and we'll write about it. We're pro-competition and we like tracking things that may challenge the status quo (eg, Arm). RISC-V is still so young that it's not in widespread use and the opportunity for that community to blow it hasn't come up yet.

There may be some technical limitations to OpenRISC v RISC-V. The people who created RV complained that OR still had branch delay slots (ew), the architecture and its software stacks weren't fully 64-bit ready, and the ISA encoding space gave too much room to immediate values, which is awkward.

Sure, I hope one day we get a chance to do a technical look at RISC-V v OpenRISC v OpenPOWER v OpenSPARC, but for now, the reason why we write about RISC-V is because we like an underdog. As Arm's CEO said, RISC-V keeps Arm on its toes, which is good for everyone. OpenRISC and OpenPOWER ain't doing that.

C.

[bazza]

Re: OpenRISC

Risc-V is the underdog, but I fear that it always will be.

I just can't see why any company would take it on as a tool to try and achieve market dominance in any existing CPU market segment. To achieve that would take a lot of money and time, and a lot of nerve, unless they already were a large incumbent in the industry.

Look at how long it's taking ARM to get into the server market; years and years of trying by various ARM licensees, and there's still very large customers who still won't even look at AMD (who are at least compatible with Intel), never mind giving a whole new ISA a try.

Nor can I see an academic collective being able to do things fast enough for it to challenge a well resourced, well practised company.

People who sell or run software for a living are collectively very conservative. Even if someone came up with a compelling, gonna-be-market-beating Risc-V offering, a large part of the existing software owners / runners would be content to wait for Intel / AMD / ARM to catch up and stamp all over it.

[Alan Brown]

Re: OpenRISC

Simple: trade wars

The USA has been attempting to stop China developing x86 and ARM via various sanctions

MIPS has its own sets of issues and the longsoong line seems to have stagnated

Power and sparc would likely face the same attempts at blocking IP flow if the USA perceives them as a threat path

That leaves the ground-up open path open

[ClarkMills]

Re: OpenRISC

From what I understand... RISC-V is open from the ground up. The others have opened up to varying degrees their legacy IP; but apparently not all of their IP. Also technology has advanced since those earlier processors were released and RISC-V has cherry-picked the best and navigated around the worst.

[bazza]

Has RiscV Got What Makes A Super Super?

I'm not convinced. What a supercomputer these days needs is SIMD cores closely coupled with fast memory interfaces and fast low latency interconnecting fabric. The CPU ISA that is used to orchistrate it all is comparatively unimportant, so long as it does not produce much heat itself.

So if RiscV wants to get into the HPC business, it'll need those things. And the problem is that getting software math kernels for SIMD cores right take a lot of very specialised care and expertise...

[W.S.Gosset]

"I wonder..."

"...hmm..."

# kill -s SIG-HPC 0

"Hoooo-WEE, look at it go!"