Write Endurance was the failure
The whole point of persistent byte addressable memory is merging memory and storage. Do it right and the persistent memory chipmakers take tens of billions of dollars per year of revenue from the DRAM makers. At the application level, this means user code can write to memory and persist information in the time it takes to do a cache flush, not the time it takes to send a write down the NVMe storage stack.
When the Micron/Intel technology only hit about 10^6 cycles of write endurance, that meant it couldn't be a DRAM replacement as seen from application software, because there had to be wear leveling even more aggressive than flash.
Which meant it was in the I/O path, not the memory path, out of the CPU, and had long latencies compared to DRAM.
It had failed at that point. I salute the Intel people who made a market for 3DXpoint anyhow. But the victory was hollow and the technology should have failed the basic sanity checks before a fab was built.