Xilinx pops a 16-core 64-bit Arm system-on-chip from NXP into its latest FPGA-based 100Gbps smart NIC

Xilinx will today launch a network card that not only offloads acceleration to an FPGA but also to an on-board NXP chip containing 16 Arm CPU cores. The Cortex-A72 Arm core cluster is expected to run Linux – Ubuntu and Yocto are supported – and act as the control plane, and the gate array as the data plane chugging through …

[Anonymous Coward]

Just like Bigfoot Networks Killer NIC, back in 2007. Back then it was for gaming, only up to 1Gb :)

[karlkarl]

That Killer NIC did look bad-ass though. Even if I don't recall it being that effective.

https://pcper.com/wp-content/uploads/2006/12/f234-card-front.jpg

[John Sturdy]

Nothing new under the sun

Moving logic into the IO controllers? Just like the mainframe channel controllers (Wikipedia says from 1957 on the IBM709).

[Anonymous Coward]

Re: Nothing new under the sun

Moving back to mainframes, just this time it's called the 'cloud'.

The prediction was right all those years back, there will only ever be need for 5 computers in the world.

[endricschubert]

In SmartNICs it is all about architecture

This is a fascinating approach not only for freeing up CPU cores in servers but more importantly in getting the overall system latency down. As the industry has been replacing HDDs with SDDs, the IO bottleneck has shifted (again back) to networking. However, having a SmartNICs per se is not fully addressing those network bottleneck issues as the overall system architecture of a SmartNIC in a server makes a major difference. A hybrid approach of offloading onto dedicated TCP cores (implemented in FPGA or ASIC), then local network protocol processing on the SmartNIC (Solarflare Onload), then TCP Bypasses such as DPDK seems to be the most efficient and most flexible approach. My 2 cents, Endric