SiFive inches closer to offering a true RISC-V PC: Latest five-core dev board includes PCIe, SSD interfaces SiFive will today unveil its latest developer board, which edges the startup closer to offering what you might consider a fully-fledged RISC-V desktop PC. The modestly named HiFive Unmatched is a follow-up to 2018's now sold-out HiFive Unleashed. If you missed out on getting an Unleashed system, here's your chance to bag an …
You have to remember that ARM is a RISC architecture as well, and some models can be vulnerable to Spectre. It's more a flaw inherent to the technique of speculative execution. The main reason RISC-V doesn't suffer from this is that it's too simple a design; but as performance demands rise, a tradeoff starts to appear between security and efficiency. Think of this: how can one produce a system that's hard to read electrically while also being able to maximize the use of limited power sources like batteries?
Not true. It was simply negligence on Intel's part or maybe even willfully inserted at the suggestion of the NSA. It's certainly possible to design an out-of-order CPU design without any security vulnerabilities or performance bottlenecks.
Intel's newest parts a supposedly secure and obviously still use out-of-order execution. Thing is, I don't trust them, and will not trust them for quite a while.
"Not true. It was simply negligence on Intel's part or maybe even willfully inserted at the suggestion of the NSA. It's certainly possible to design an out-of-order CPU design without any security vulnerabilities or performance bottlenecks."
Really? Then name at least one, please. Remember, even RISC architectures like ARM are prone to Spectre.
> Can RISC architecture offer more mitigation strategies to Spectre type attacks than CISC can?
Short answer: No.
Long answer: Still No.
Spectre-type vulnerabilities are caused by speculative execution leaking cache information. That, in turn, has nothing to do with the chip architecture, since both RISC machines and CISC machines employ speculative execution.
>since both RISC machines and CISC machines employ speculative execution
A CISC is a RISC with specialized microcode (that's an Intel processor, for example). Implementing complex logic efficiently requires a regular design, just throwing gates together leads to all sorts of design and timing issues. A RISC is inherently regular so you'd build up a more complex design from its basic building blocks.
AMD were doing some amazing stuff with their 29000 seires RISC processors before they copped out and just focused on the x86 ("it was where the money was"). Seculative execution works best with a large pool of registers and they'd started producing units that were also able to rename them, essentially allowing dynamic reconfiguring of the processor to produce several speculative execution paths. I don't know how this would map to a Spectre type bug; its possible that because they're not working in cache but register space that you might not be able to tell the execution paths since there would be no cache misses.
(I wonder if AMD's RISC expertise got dusted off for use in their graphics processors?)
It's more complex than that and RISC is a bit of a misnomer.
Intel's i960 wasn't bad back then. Popular on RAID controllers. They also obtained DEC's Strong ARM family, most of which were sold to Marvell. They might still have an ARM based comms chip and some sort of ARM licence.
They overfocused on x86 and then HPs inspired Itanium which seems to have been illfated. Shortest XP support?
Not really. Spectre type attacks use a fundamental flaw in the processor design related to speculative execution. RISC processors typically utilise similar speculative execution approaches, so in principal could be vulnerable to the same attack vectors. It all depends on whether the designers of the chips have addressed this issue and implemented a mitigation strategy into the silicon.
Most of the spectre attacks aren't architectural attacks (RISC/CISC/x86/PPC/ARM), they are chip engineering design. They attack techniques that the engineers who do the layout of CPUs use to improve performance. Things like caches, out of Order Execution, all that fancy shit is not architecture dependent. They are techniques an engineer can use on any (or most) underlying architectures. It's just that the shorcuts that Intel engineers took to improve performance have tended to be less well implemented (e.g. heartbleed, where Intel wasn't checking if the process that was reading privileged memory was allowed to read privileged memory after speculatiive execution paths were rejected. It was an implementation error where they didn't perform this extra privelege check).
It should also be noted that ARM, PPC, SPARC that all have their own variants of spectre-type attacks are all RISC architectures.
And a further note, x86 really isn't CISC anymore. It's front-end is CISC, but once the instructions get fed into the CPU, they get RISCified. That is, they get 'decoded', are split up, into what Intel call micro-ops, that are RISC instructions by another name. So the actual logic processing that is done in an x86 CPU in response to user-issued instructions is done on a RISC core.
Not especially likely, as that would expose micro-architectural details that you probably want to be able to vary from model to model, such as number and structure of pipelines and size of re-order/re-name buffers.
Has been done before though, twice: Transmeta did essentially exactly that, replacing the x86 decode logic with a software dynamic compilation system that targeted an in-order VLIW processor to do the work. Nvidia's "Denver" cores and follow-up (as seen in the Nexus-9 tablet and several of the car-AI modules) do a very similar thing but for an Arm source-instruction-set.
Both work nicely on loopy, numerical code, but quite poorly on large, non-loopy code like user interfaces, database engines and operating systems.
Interestingly, Dave Ditzel was involved in both of those designs, and is now founder of Esperanto, a RISC-V company.
In addition to what @_andrew said, it would also not be able to run any existing x86 compiled software. Every existing piece of x86 software would not be able to run on such a machine, as their compiled executable code is targeted at the CISC front-end, so just wouldn't run on such a machine. Thus eliminating the biggest advantage x86 has over - allegedly superior - architectures that don't have this massive backcatalog of software it can run.
In theory it would just require a recompile in most cases, however considering even critical software tends to lose maintenence support quickly in lieu of selling a new and improved (allegedly) version, the chances of your favourite/critical software getting the care of a recompilation is pretty much nil, as the vendor would rather you pay for this new software that runs on the new architecture. Even if the vendor was happy to recompile, it's likely that it depends on libraries from other vendors that can be a decade old, and they may not even be around let alone willing to compile decade-old libraries.
If the Raspberry Pi people were really interested in an open chip architecture they would never have chosen Broadcom as a supplier. While RISC-V might be an alternative in the future, ARM is currently the better offering because there are so many suppliers: Broadcom, Qualcomm, Samsung, Mediatek, Huawei, etc.
Currently the RISC-V is of more interest as a Server and people investigating RISC-V, rather than very low power general purpose board with a wide range of OS, software, application use and from one-off hobbyists to industrial integrators.
You could build a desktop PC out of the Unleashed and its expansion kit, and so you should be able to do the same with an Unmatched system.
Do you know if that facility/utility/ability is long ago known and extremely well commanded in novel virtually activated systems of remote practical overall control ?
Do you know how that is easiest done/best shown/realised other than resulting in a Quantum AI Leap Step into Virtual Futures and AIdDerivative Trade Activity Sharing Universal Secrets for the Much Bigger Picture Full On ACTion Shows Servering and Savouring the Infinite Flavours and Hellish Delights Afforded Worthy Success with Instant Access Granted to Heavenly Excess. What is your AIDriver Master Pilot Presenting You to View and Populate/Inhabit/Reign In. :-)
* Do you deny things are so fraught and rudderless, both virtually and practically everywhere, and thus the Great Intervention Invention for Guaranteed Grand Global Master Board Resets.
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