Re: He who laughs last ...
One of the dirty secrets of CPU design over the last more than thirty years, is that all the clever stuff is actually redundant in the long term. It’s a bunch of insanely clever workarounds that just won’t be needed once a very specific key technology problem is solved: memory interconnect speed. Intel, AMD and ARMs technical lead and “moat” isn’t forever, it’s dependent on that one problem.
Just making a CPU that has the basic execution units, even in whatever parallel microarchitecture, with whatever Deep Learning accelerators, that’s just not that hard. It can be done by any good engineering team with less than a hundred engineers in a couple of years.
Treble that, at most, for really optimised local power consumption.
No. What’s hard is: out-of-order execution. micro-op optimisation to make that efficient. Branch prediction. Translation lookaside buffers. Cache architectures with snooping.
The common theme is that they are all workarounds for the memory wall problem.
Figure out a transport interconnect from external RAM to CPU that’s high-bandwidith without drawing insane amounts of power, and absolutely the first thing that will happen is *removing* all those clever widgets from CPUs, massively increasing core count by replacing the silicon area and power used by the caches, and hooking it straight into main RAM.
Obviously, I’ve got no idea how to solve that problem. Perhaps optical-RAM-to-CPU interconnect. Or spin-wave-transistors (which don’t drive capacitance load). Perhaps in-memory-computation.
But at some point, maybe a decade away, or even two, it will be solved. Then, almost overnight, Intel, AMD etc just own a bunch of IP that consumes 95% of silicon area for little benefit.
Given that owning such CPU IP forms a major part of the West’s strategic advantage and leverage over China, that’s really something to think about. Being only a single brainwave insight away from a major strategic shift that will likely happen within ten or twenty years. I’m not talking about FTL travel here, just a board-level signalling technology that breaks no laws of physics.