Xilinx's high-end Versal FPGA is like a designer handbag. If you need to ask the price, you probably can't afford it

Xilinx will today announce an FPGA that is a little bananas: the Versal Premium, aimed at cloud builders and telcos. It's the sort of component that if you need to ask how much it costs, it's probably not for you. Instead, you need to specify how many you need, and the price will be calculated from there. It includes a …

[EVP]

How much does it cost?

[Steve Kerr]

If you have to ask, you can't afford it :)

Beer is currently still affordable

[Sgt_Oddball]

YBMV*

That entirely depends on your watering hole of choice...

Northern monk in Leeds was selling a beer for £1,000... Its now dropped in price abit to a much more reasonable £150.

Still mines the pint of Sam Smith old brewery. Just topping £1.53 at last checking (yes. That's 3 whole pints with change to spare from a £5)

[Steve Todd]

“ That's enough to simulate your own CPU core, though that's not really the intended use case.”

You can design a CPU with as few as a couple of hundred LUTs, so it’s probably massive overkill for all but bleeding edge designs.

[Mike Shepherd]

High-level

"...high-level languages, such as C/C++, or low-level SystemVerilog and the like"

Verilog / SystemVerilog are high-level languages, just like C and C++.

[Cynic_999]

Re: High-level

"

Verilog / SystemVerilog are high-level languages, just like C and C++.

"

I was thinking the same. All my Xilinx designs in the 1990's were done using schematic entry. I designed a CPU that mimicked a Z80 in a Xilinx (but fewer cycles per instruction). Also had a few peripherals so it was essentially a SoC - just needed ROM and RAM.

[genghis_uk]

Re: High-level

I remember doing something similar - just because we could... Ahh, the good old days when engineering had some play time!

Can't remember what device - either a 5200 or a 4k I think (mid to late 90's)

[bazza]

Re: High-level

I used to do schematics targetting Atmel FPGAs. Ah, those were the days.

I think there'd be a good use for the opposite; something that takes vhdl / verilog and shows the developer what the equivalent schematic would look like. That'd probably be a good thing for highlighting the massive inefficiencies that can spring from carelessly written vhdl / verilog...

[M. Poolman]

Re: High-level

Been a long time since I thought of C(++) as high level!

[bazza]

Re: High-level

Verilog / SystemVerilog are high-level languages, just like C and C++.

Language level aside, it's the standard libraries that make the difference. I don't think there's a malloc() in Verilog or VHDL...

[Dom 3]

Would they sell one to Oprah?

[Snar]

But

Can I get a one to one exchange on bog roll?

[ClockworkOwl]

Re: But

Only medicated!

[Johnny Canuck]

Goody

Can't wait to try out my 8 bit MC6809 on it!

[bazza]

Re: Goody

That'd probably count as one of the worst cost / benefit ratios ever. I say, do it!

[bazza]

This is Getting Ridiculous

The fashion in FPGAs these days is to litter the chip with a variety of hard peripherals that the designers think developers will find useful. This one is no exception; tons of DSP, crypto, I/O of all sorts, CPU cores.

The thing is, taken to extremes, this trend will result in people using verilog / vhdl to marshall data in and out of these built in peripherals, and won't really do anything else with the data. At which point, what's the bleedin' point of it being an FPGA? Why wouldn't one skip the difficult, cumbersome vhdl / verilog part, and simply have a few lines of C running on a proper CPU marshalling data in / out of the same built in peripherals, achieving the same net result?

With this one you're probably able to stand up a full network connected video transcoding streaming media server, without really doing any actual data processing in VHDL, and you'd probably not need the ARM cores for that either. If silicon dedicated to LUTs and logic got handed over to more DSP cores instead, you'd probably have an even more useful chip, but then it'd not be an FPGA at all.

[ee_engineer]

Re: This is Getting Ridiculous

Logic is hardened as a function reaches a tipping point. When most users need function X (e.g. DSP) it gets hardened as it is more efficient that building that function out of logic.

With this generation of technology there will be a range of families and parts with different ratios. E.g. Some will have the AI engines, some won't, so customers who need more/less DSP/LUT/Memory/AIE can choose the right part.

Parts are targeted for certain market segments.

>The thing is, taken to extremes, this trend will result in people using verilog / vhdl to marshall data in and out of these built in peripherals, and won't really do anything else with the data.

(1) The "built in peripherals" are not the same. The FPGA is massively parallel, with far more banwidth than a CPU (2) The Versal has a built in NOC which manages dataflow, so you don't have to use all your LUTs on interconnect as you suggest.

>Why wouldn't one skip the difficult, cumbersome vhdl / verilog part, and simply have a few lines of C running on a proper CPU marshalling data in / out of the same built in peripherals, achieving the same net result?

For your FPGA application, you would get nowhere near the same performance/power efficiency on FPGA vs cpu.

See example here:

https://www.linkedin.com/pulse/accelerating-decision-tree-based-predictive-analytics-winterstein/?trackingId=jRNvxSSnQt%2BHbbjOVXWabA%3D%3D

For one example, the performance is x764 vs CPU for the particular FPGA used.

[TrumpSlurp the Troll]

Asking for a friend

But can it run Crysis?