128-bit simd units
Text says 128-bit simd units in a list of per package things. I assume these are per core?
Ampere will today tear the covers off Altra, its 80-core 64-bit Arm N1 processor for cloud and hyperscaler servers. Meanwhile, Marvell announced additions to its Octeon TX2 family of Arm microprocessors, including a 36-core 64-bit Arm part, and Xilinx will tout its Alveo U25 network card. These announcements were timed for …
"We asked Ampere to explain how it has tackled any Spectre-style side-channels lurking in its out-of-order execution pipeline. "We have full hardware mitigation for Spectre and Meltdown designed into Ampere Altra," Wittich replied."
... that what he meant to say was hardware mitigation for that style of leakage...
It seems to me that they are about a year late into the game.. AMD provides x86 compatibility with more performance.. and they will ship "mid 2020".. so they can barely compete with 2019 product and obviously not 2020 product.. so they will have to compete on price.
I fully expect their integer performance to be low.
Anyway, all competition is good, and I hope the best for them.
Link to cloudflare´s analysis:
Wasn't Cloudflare super excited about Qualcomm's ARM CPU? Then that CPU just got dropped entirely.
Kinda curious what might make these ARM server CPUs better when it seems every ARM server cpu has failed(probably half a dozen big attempts so far? Even AMD was all in on ARM for server at one point).
Seems ARM has about as much trouble scaling up(200W+ server cpus?) as x86 has scaling down.
RISC-OS can only use a single core. There is no MP code in it, and adding it would require a major rewrite. In addition, it is only 32-bit, and I'm not 100% certain that the 64-bit ARM processors still have 32-bit instruction modes.
When I first learned the in-depth technical aspects about MP for Amdahl UTS (a UNIX SVR2 port initially) running on a mainframe, we were told about just how much of the kernel had to be changed to add spin-locks on all of the kernel structures, and the number of man-years that it took.
RISC-OS is more simple, but the effort would still be significant, especially as the process model for RISC-OS does not use the hardware address protection that the ARM provides, so the lack of process address space separation would also be a major problem.
Ampere claimed an 80-core-per-socket dual-socket Altra overclocked to 3.3GHz is on a par with a 2.25GHz 64-core-per-socket (128 threads per socket) dual-socket AMD Epyc 7742, in terms of estimated SPECrate2017_int benchmarks.
Note: not safe for ears!
Big Stinkin' Deal!
We've has 128 bits wide for almost 5 years now on our 575 TERAFLOP Combined CPU/GPU/DSP super-chip running on 60 GHz GaAs hardware!
But that's NOT or biggest and BADDEST CHIP .... That would be our TWO TERAHERTZ GaAs 19.2 PETAFLOP MONSTER CHIP which is now part of the most powerful supercomputer ever made! We have more CPU/GPU/DSP horsepower than ALL of the Top-500 + our old 119 ExaFLOP monster COMBINED !!!
Now number-crunching the "Secrets of the Universe" in a deep underground facility in the Cooooooold Far North Mountainous Regions of British Columbia, Canada!
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