A carbon-nanotube RISC-V CPU blinks into life. Boffins hold their breath awaiting first sign of life... 'Hello world!' “Hello, World! I am RV16XNano, made from CNTs.” That’s the friendly message emitted by a RISC-V-based chip made entirely out of carbon nanotubes (CNT) and revealed on Wednesday. More than 10,000,000 CNTs were used to form 14,702 CMOS carbon-nanotube field-effect transistors (CNTFETs), arranged in 3,762 digital logic blocks, …
CNT based sensors seem to work well but yes this is the first time such a complex structure has been made.
Incidentally it is said that the very first CPU was made by cutting and pasting physical pieces of film, to make the mask that was later optically miniaturized and used.
Yup, just like you can use an old style photo enlarger to make bigger copies of negatives onto paper so you can use different optics to dial a source down in size. It was a pretty obvious route for at least the initial work.
Disclosure: in my Honours and PhD I printed a LOT of pictures, though I did have technical help for a decent proportion. But I have earned my spurs in photo printing in a darkroom.
Sometimes the structure of the carbon atoms results in structures that have unwanted metallic properties, such as high conductance. This can lead to current leakage and faulty chip operation, which you don't want in a processor.
One of the more interesting aspects of the research is exactly how they countered the metallic carbon nanotubes. They mapped out every possible scenario where the metallic carbon nanotubes interfered and ran simulations to find all the different gate combinations that would be robust or wouldn’t be robust to any metallic carbon nanotubes, which they then built into the chip design automation.
> Carbon nanotubes are tricky to work with. Sometimes the structure of the carbon atoms results in structures that have unwanted metallic properties, such as high conductance.
Flaws like high conductance can make the resulting chip look silly. Worse is when only one end of each alternate carbon nanotube is attached to the silicon, leaving a loose end to stick up: this is even cilia.
If I'm understanding the paper right, 10,000 digital logic gates were in the die spec of which 3762 wound up being used.
The process sounds like an FPGA type design.
Maybe 38% transistor utilization is good for FPGA; it isn't good at all vs silicon.
It also isn't clear how well the utilization can scale up - really depends on the type and nature of the failures causing the low utilization.
Cool, but a semi factory equivalent of Heathkit.
Modern chips comprise hundreds of millions to billions of functional transistors.
So, you're telling us that this new technology, at an early stage of development, is not yet competitive with our existing half-century-old technology?
Well, I for one am shocked. Shocked, sir. I demand we cancel all further research into carbon nanotubes and obliterate all mention of it from the history books.
Not quite - FPGA is kind of like lots of devices that can be joined together in a miriad of ways as you choose, This is an array of device some of which may work, and those working ones are then wired together to make the final working circuit. Think of it as a massive breadboard that is populated with a load of components bought from a dime store. The components are fixed in before you can test them so you have to use whats there.
Distantly recall an idea to use vertical CNT arrays as nanoscale memory.
The plan here was similar, fix in place then lay down the interconnects and R/W logic, but ion implant Zn or some other metal so that one metal atom ends up in each tube, then use standard wear leveling and error correction so more than one CNT stores each bit, yet also acts as a CRC for another elsewhere.
The Register 
Biting the hand that feeds IT
Copyright. All rights reserved © 1998–2025
