IBM hears the RISC-V kids partying next door, decides it will make its Power CPU ISA free, too

IBM is planning to allow chip designers around the world to freely create OpenPower-compatible processors. The aim is obvious: to encourage the implementation of OpenPower CPUs, and get more Power-based systems out into data centers and the wider world. It also means engineers can customize their own OpenPower chips to run …

[Anonymous Coward]

Needs a better name

POWER is such a naff name - far too much testosterone in the room when they came up with that.

They need something to emphasize the Free/Libre aspect so FLOWER rather than POWER.

And it sounds perfect for Operational Technology solutions so openFLOWERpot it is then.

[Icon: is it going home time yet?]

[Anonymous Coward]

Re: Needs a better name

For you, sir, yes. For you the bar is closed for the night.

[Anonymous South African Coward]

Re: Needs a better name

Bob the Angry Flower.

Look it up.

[Brian Miller]

PowerCarrion, Vulture Architecture

"It means, say, El Reg would be free to design and sell an OpenPower processor..."

Would this mean branch prediction for roosting vultures? Roadkill cache for munchies? The mind wanders...

[martinusher]

Complements the RISC

The RISC-V architecture is effectively a distillation of generic RISC designs into one common design. Opening up the Power architecture promises to do the same for CISC but we'll have to wait and see if this is successful. (RISC designs will always be with us because they are lean enough to incorporate economically into FPGAs, CISC architectures are not.)

[Anonymous Coward]

Re: Complements the RISC

Do you really consider POWER more CISC than RISC?

[James Anderson]

Re: Complements the RISC

My take is that is really 4 RISC instruction sets -- One 32 bit little endian, One 64 bit little endian, one 32 big endian and one 64 bit big endian.

IBM dragged along a lot of baggage to keep backward compatibility with AS/400 and RISC/6000.

IBM failed to grasp the market when they had the opportunity. Along the way they lost Apple, Xbox, Sony and Nintendo. You would have thought 300 million odd games consoles plus 4 million MACs a year was an attractive market worth keeping.

[chasil]

RISC-V criticism

The author of this post may exhibit bias, but perhaps the architecture is not as well-designed as some would hope.

https://gist.github.com/erincandescent/8a10eeeea1918ee4f9d9982f7618ef68

[Anonymous Coward]

Re: Complements the RISC

Power is a CISC architecture? Interesting. Next you'll be telling me x86 is still a classic CISC processor design....

RISC-V is effectively a low complexity implementation of a RISC design - to compete with SPARC/MIPS/POWER/ARM/x86 RISC implementations, the complexity has to increase (i.e. longer pipelines, speculative execution, caches etc) to prevent memory access and branching limiting performance. The lack of complexity maybe good for power efficiency, but it limits the ability to scale clock speeds and IPC.

[Bruce Hoult]

Re: Complements the RISC

RISC-V is not an implementation, it is an ISA.

The currently available implementations of RISC-V are low complexity, but you can be sure higher complexity higher performance implementations are in development at a number of companies -- most publicly at present Esperanto Technologies (who picked up Chris Celio of BOOM fame) and Alibaba.

[Anonymous Coward]

Re: Complements the RISC

"The currently available implementations of RISC-V are low complexity, but you can be sure higher complexity higher performance implementations are in development "

I don't doubt there will be performance improvements. The thing is they will likely only match high-end ARM performance rather than begin to compete with POWER/x86 with significantly more complexity.

And is it worth the effort of making ARM/RISC-V chips that are able to compete on performance with POWER/x86/EPYC given existing players (Itanium/SPARC) are dropping out due to cost?

Phoronix did a review of available ARM vs POWER vs Xeon vs EPYC - while I accept there are some mitigating factors, the performance difference between the ARM cores and the POWER/Xeon/EPYC isn't going to disappear quickly and these tests largely ignored single thread performance where ARM is weaker still (single thread is around 20% of the performance of a Xeon/EPYC at simlar clock speeds which is similar to where it was 10 years ago).

https://www.phoronix.com/scan.php?page=article&item=rome-power9-arm&num=4

[Alan Brown]

Re: Complements the RISC

Horses for courses.

The single biggest problem with multithreading and weak singlethreading isn't the CPU, it's the programmer - WE are the ones who have difficulty writing multithreaded code and have always done so even in the days of Occam, so we try to make up for it by using faster single cores.

Perhaps this might change (yeah right) or perhaps someone might come up with some kind of breakthrough to make parallel coding much easier.

The human brain doesn't clock very fast, but its computation rate is pretty good regardless.

[Anonymous Coward]

Re: Complements the RISC

"The lack of complexity maybe good for power efficiency, but it limits the ability to scale clock speeds and IPC."

No speculative execution means no SPECTRE related attacks, and a much better chance of securing the processor.

[Peter Gathercole]

Re: Complements the RISC @martinusher

It's quite debatable whether POWER is really RISC, although IBM came up with a couple of really bad bacronyms - "Performance Optimization With Enhanced RISC", and "Reduced Instruction Set Cycle-time" (this one is seriously bad, and goes back to the RISC System/6000 days, when IBM actually thought it could redefine RISC).

The POWER ISA has more instruction types and addressing modes than many CISC designs, although it does run instructions at or near the clock speed (or faster when you consider super-scalar execution), and does have a large register set, which are, or were, some of the defining concepts for a RISC processor.

[Anonymous Coward]

Re: Complements the RISC @martinusher

"It's quite debatable whether POWER is really RISC"

And if you get into that debate, the reality is that all commercial CPU combine portions of both design concepts (SIMD being the best example for a CISC instruction utilized in a RISC architecture) but that RISC has decisively won.

The discussion around commercial CPU's being CISC/RISC is largely academic - if a design choice allows for performance (IPC/power/etc) it will likely be adopted unless power is an issue at which point it appears when the process node improvements allow it.

[Michael Wojcik]

Re: Complements the RISC @martinusher

"Reduced Instruction Set Cycle-time"

Phil Hester's formulation was actually "reduced instruction set cycles", defined as "optimal ... path length times cycles per instruction". See "RISC System/6000 Hardware Background and Philosophies" in IBM RISC System/6000 Technology, IBM SA23-2619, published 1990.

As Hester points out in that piece, the definition of RISC and RISC-versus-CISC was already a tired topic then (30 years ago). While you may not agree with Hester's argument about why POWER (IBM marketing was already pushing that acronym) is a RISC architecture, he was certainly correct that "a reasonable melding of RISC and CISC concepts [became] the direction for many future RISC designs". And for supposedly CISC designs, too.

[Peter Gathercole]

Re: Complements the RISC @Michael Wojcik

I have a copy of that document. I was quoting it from memory, as it is at home, and I was away when I wrote the post.

[Anonymous Coward]

OpenPOWER drank the little-endian koolaid

From a secret big-endian fan.

[Anonymous Coward]

Re: OpenPOWER drank the little-endian koolaid

My low level knowledge may be out of date, but the endianness of PowerPC processors used to be selectable at startup.

[whitepines]

Re: OpenPOWER drank the little-endian koolaid

POWER is actually bi-endian, apparently one can even switch endianness at runtime per process.

Crazy stuff.

[John Savard]

Good News for Me

I like this because PowerPC has condition codes, and so it's easier to understand and program than RISC-V as far as I'm concerned.

But what IBM should have done was, long ago, when the Macintosh used PowerPC chips, to have bought Apple.

During the short time, of course, when Steve Jobs was at NeXT; otherwise, like Greenland, it would not have been for sale.

[Anonymous Coward]

Re: Good News for Me

I imagine at that time what stopped it was the same thing that did for IBM as a PC maker; the mini and mainframe divisions not wanting competition for some business from within the company.

When the Mac first appeared I pointed out to my boss that the SE/30 had as much compute power as our VME workstations, at a quarter the price. His reaction? "Don't tell anybody."

[Citizens untied]

Re: Good News for Me

Not exactly a big Apple fan, but can you imagine a "Man in the High Castle" version of the iPhone if IBM had bought Apple *shudders*.

Though, they may have revived "the Little Tramp" for the ad campaign.

[Anonymous Coward]

Power is a great architecture. Many of the stupid legacies of the x86 can be forgotten!

For the arch to really fly, IBM would do well to look at the complaints against Wintel and provide an alternative. Office use is after all still the biggest market after mobile phones. Makes me shudder how far in bed with MS my own employer has got.

I’ve said this before but another untapped market would be the bedroom computer. Apart from the raspi, nobody makes Atari/Amiga style boxes anymore at the right price point. A ps5 equivalent with proper keyboard, ui, and tools wrapped around a games system would be immensely popular.

[Ken 16]

Performance / Cost

PowerPC is a great architecture and I've liked working with it since it first offered 64-bit computing (p4/2000?) but for the last ~10 years it's been possible to get equivalent performance for less from Intel. Aside from special purposes, like routing data between GPUs on 'supercomputers' or running some inherently single threaded computations then x86_64 cpu is good enough. I don't see OpenPOWER getting enough traction to drive costs of competitive server boards down.

[Anonymous Coward]

Not my area of expertise

Would it be possible (practical) for Apple to ditch ARM and switch to OpenPower?

It sounds like Apple has already deviated quite a bit from the base ARM design... and, Apple shifted to its own GPU already.

ARM (Qualcomm) hasn’t scaled well to run Windows. Apple is supposedly attempting to use its A Series chips in laptops and desktops... Could they be experiencing the same problem? ARM wasn’t designed to multitask well...it was designed for battery efficiency.

Could this a way for Apple to go royalty free? And, bring everything in-house?

Apple basically runs Unix. Seems like a good fit...

[calonddraig]

Re: Not my area of expertise

Oh the irony of Apple going back to Power... I still have an old desklamp g4 as the most comfortable terminal I've ever used, and a powermac g5 to mess around with legacy apps I still support. I can't ever see Apple going back to Power...

[Anonymous Coward]

Re: Not my area of expertise

"Apple basically runs Unix."

<soapbox> MacOS *is* UNIX: https://www.opengroup.org/openbrand/register/brand3648.htm </soapbox>

[Anonymous Coward]

Re: Not my area of expertise

I suggest you use the soapbox for kindling. He was right. It does basically run Unix. But MacOS is a lot more than the core operating system, and to say MacOS is Unix is to confuse the whole for the part.

If MacOS were Unix, I doubt they'd sell many Macbooks.

[Velv]

Niche Market

I guess there will be a market for custom big installations, however the drive to virtualise and cloud in "x86" world means the vast majority of workload is now processor agnostic.

Unless they plan on producing a hypervisor for OpenPower I just don't see a market

[Giovani Tapini]

Re: Niche Market

Many IBM machines that use power do indeed have a hypervisor of sorts, at least a hardware abstraction layer. This however is not open sourced.

[whitepines]

Re: Niche Market

Not quite, the abstraction layer appears to be OPAL:

https://github.com/open-power/skiboot

As far as a hypervisor, what exactly is wrong with using (accelerated and nested capable) KVM?

Both of those parts are open source BTW.

[Anonymous Coward]

Re: Niche Market

The PowerVM hypervisor is interesting. It's not Open Sourced, but it does include Open Source software! (I'm sure IBM are complying to the GPL)

This is because there is a Linux kernel running the hypervisor (at least the Flex Service processor), but it is so locked down that you can't see it.

The PowerVM hypervisor is initialized from the Flex Service Processor (FSP), and at one of the installations I supported, the very unusual systems had the FSP unlocked so you could telnet (yes, telnet) in to it, to find that it was a fairly complete Linux installation, complete with a copy of crack amongst other things.

Whether the actual hypervisor itself is Linux is unclear, but I would not be surprised if it was.

In case anybody wondered, the 'alternate side' of the FSP code (allowing for easy roll back after an update) is a second full file tree, linked in as a sub-directory under root (/), and when you switch, it fiddles with the root inode to swap the two file trees over (I never exactly worked how it was done, but I can guess).

The lower cost OpenPOWER systems do not use the PowerVM hypervisor, but OpenPOWER Firmware that is compatible with tools that control VMware systems, allowing OpenPOWER systems to be more easily integrated in to Intel environments. OpenPOWER Firmware is open source according to this page.

[/dev/null]

"it's a RISC-like architecture that grew out of PowerPC"

No, PowerPC grew out of POWER.

First POWER implementation (POWER1) hit the market in 1990. First PowerPC systems (PowerPC 601) were released in 1993. The two have had a complex and intertwangled history since then though.

[Peter Gathercole]

Re: "it's a RISC-like architecture that grew out of PowerPC"

They've gone back to POWER branding.

There has a hiccup with PowerPC around the PowerPC 620 processor, and most of the current processors are derived from the Apache 64 bit POWER processor (also known as RS64) developed for the Power AS/400 systems at Rochester, Minnesota, not Austin. Texas.

Power4 was a converged processor that provided supersets of both PowerPC and earlier POWER processors. The last PowerPC branded processor, the 970 and it's FX, GX and MP variants was itself derived from Power4.

[anonymous boring coward]

Some real quick decision making there from IBM..... (Sarcasm)

[Anonymous South African Coward]

One thing is for sure - the market just got very interesting.

[Anonymous Coward]

Pot calling Kettle

"That led to some unsavory types getting their hands on Power-based technology, such as manufacturers of surveillance equipment based in the Middle Kingdom."

- as opposed to -

That led to some heroic types getting their hands on Power-based technology, such as manufacturers of surveillance equipment based in the United Kingdom ?

[fobobob]

Hmm, no Snap! jokes yet.

We've got the POWER?

[fredesmite]

POWER still isn''t dead ?

No one uses it but IBM