back to article On the first day of Christmas, MIPS sent to me: An open-source-ish alternative to RISC-V

AI biz Wave Computing on Monday told the world it intends to open source the latest MIPS instruction set architecture (ISA) in the hope that fosters the development of more RISC-based custom chips. The outfit acquired MIPS, the fabless CPU design firm that had been sold twice before since 2013, back in June with the intention …

  1. Mage Silver badge


    But maybe doomed without clearer licencing and at least one open source CPU HW reference design as a starting point for CPU developers?

    I can't see how simply allowing the instruction set to be freely used as "open source" (which licence?) makes a big difference. See 8080 vs Z80, 6800 vs 6502, various clones of 8088, 80486 etc that didn't exactly have a licence.

    As article suggests, it smacks of PR and desperation.

    Perhaps they need to "open source" ALL the MIPS IP they own to "save" the platform and encourage the development for their "AI" applications.

    Even apart from RISC-V, the MIPS has lost out to ARM on almost every area and x86-64 on servers & workstations.

    My coat has the Z80 instruction set booklet in the pocket.

    1. _LC_ Silver badge

      Re: Interesting

      I think this is only going to be of interest in the embedded market.

      MIPS has a VERY RUDIMENTARY instruction set. While it can save you a few transistors, it certainly won't win any trophies in the performance department.

      1. Def Silver badge

        Re: Interesting

        Isn't MIPS the architecture that actually executes the instruction following a branch due to pipelining issues?

        1. Marco van de Voort

          Re: Interesting

          Yes. MIPS traditionally had a delay slot. MIPS-X even two.

          P.s. the Microchip 32-bit architecture is also MIPS. (but of course with the acquisition of Atmel and its SAM ARMs, it now has two 32-bit architectures in one house)

        2. _LC_ Silver badge

          Re: Interesting

          I'm not sure that you can blame this on "pipelining issues". It is easier to implement (saves a few transistors).

          It's called "Delayed Branching". Many architectures used to have this (HP PA-RISC, for instance), but it got eliminated after a while. You'd mainly find only NOPs in the "branch delay slots" anyhow, as the compilers didn't like it much.

          1. Wilseus

            Re: Interesting

            I can't really see why compilers don't like it much, back when I used to write games for the original PlayStation I wrote a bit of hand crafted MIPS assembly and coding the delay slot was ridiculously simple, you can usually just swap the branch with the last instruction that comes before it. I can't see why that would be difficult for a compiler to do.

            1. _LC_ Silver badge

              Re: Interesting

              I would agree. Yet, I came to see only NOPs on HP-PA.



              [Pathlengths of SPEC Benchmarks for PA-RISC, MIPS, and SPARC]

              we can deduce, that MIPS also uses NOPs frequently to avoid load stalling:

              "For MIPS, it shows total instructions minus the NOP instructions used in place of load-use interlock cycles.


              MIPS load-use NOPs have been subtracted out, since we are not comparing register load-use stalls for PA-RISC and SPARC."

        3. bombastic bob Silver badge

          Re: Interesting

          "executes the instruction following a branch"

          as I recall it's referred to as a 'guard' instruction and can sometimes be taken advantage of by the compiler. But as often as not it'll be a 'nop'

          just as a reference, several devices that were used for Wifi access points about 10 years ago (like Linksys) used MIPS rather than ARM. So OpenWRT was designed for MIPS, particularly Broadcom's MIPS CPU, back when it was first released.

    2. DialTone

      Re: Interesting

      Totally agree about opening up the IP.

      Back when Imagination still held the reins, I did register to download the MIPSfpga SoC core from their student programme (as a hobbyist interested in FPGAs) only to have my download request rejected as I did not have a student email address.

      While that would have been relatively easy to spoof, I gave up at that point as it became obvious that the "freely available educational version" was nothing more than a marketing stunt and I decided to either write my own ISA or look at a truly open platform (such as Risc-V).

    3. Voland's right hand Silver badge

      Re: Interesting

      Even apart from RISC-V, the MIPS has lost out to ARM on almost every area and x86-64 on servers & workstations.

      Except routers and WiFi access points. Arm has started showing up lately, but on the overall it remains MIPS territory through and through.

    4. Daniel von Asmuth

      Re: Interesting

      Could we ask HPE to Open Source their AXP architecture?

      An Instruction Set Arrchitecture is repaltively simple. It is de tailed design of processors like R10000 that is muh more omplex, so the argument that it has been proven in practice makes sense. So you're allowed to make your own 'implementattion' of their ISA. But then, their hardware design is protected by numerous patents....

      Guess if you own a fab, you could just buy SGI.

  2. Anonymous Coward
    Anonymous Coward

    Wave Computing is banking on the fact that MIPS hardware is still widespread in the market, with more than eight billion MIPS chips shipped.

    Which now mostly resides in landfill, past performance is no guarantee of future success.

    1. _LC_ Silver badge

      Well, they are in Routers, Set-top boxes and such. This isn't necessarily bad, as the embedded market it huge. Yet, as previously stated, MIPS is unlikely to win any trophies in the performance department. I don't think that anybody is seriously doubting this. Therefore, the path is clear.

  3. Anonymous Coward

    Generic stupid comment

    But will it run Crysis?

    1. eldakka Silver badge

      Re: Generic stupid comment

      I see your stupid and raise it:

      Is it any good at bitcoin (insert other blockchain system here) mining?

  4. amanfromMars 1 Silver badge

    Inalienable Right Ways for a Real Immediate Change of Future Direction

    "If you want to maintain patent coverage, you need to certify your implementation," said Swift. "If you don't, you're on your own."

    In layman's terms, ... Eat your own cookies to proof future programming stable and exciting.

    How very Intriguing ..... and Wonderfully Engaging.

    Thanks for all the Core Intel, El Reg.

  5. chuckufarley

    Thanks to smart phones, networking hardware, storage controllers...

    ...and other technology commodities chips designers have gotten used to the idea that businesses are willing to hand over large amounts of money to use their kit. It seems to me that if a company really wanted to shake up a market they would do a lot more to lower the barriers of entry into that market. "Open Source" CPU designs might let companies with big budgets take their business in a new direction. However I have not seen a single product from a start up or boutique shop using them. I have read about ideas and heard investment pitches but I have not seen any real world products.

    Don't misunderstand me though, I think that anything the industry does to make technology more accessible is in the best interest of the business and humanity. So I see this as a step in the right direction. I know they need to make money off of the IP they have created.

    On the other hand, if this isn't last stop on the Moore's Law Bus then you can at least see it from here. I predict that the "Open Source" CPU company that has the lowest cost to market for small businesses and start ups over the next 5 years will be the company we read the most news about the following 10 years.

  6. John Savard Silver badge

    Chinese Designs

    Some homegrown Chinese chips used the MIPS instruction set without a license, and thus couldn't be excported until a company with a license started handling them. This change might be useful there. Next would be the Alpha...

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