back to article Third NAND dimension makes quad bit bucket cells feasible

Error-checking code use is so much easier with 3D NAND than previous planar NAND that capacity-lifting quad-level cell technology becomes more feasible. The use of error-checking code (ECC) technology involves adding redundancy to stored data by using an algorithm to work out how many bits to add and use. Block codes work on …

  1. Duncan Macdonald

    Endurance ?

    The higher the number of bits per cell, the worse the endurance (number of write cycles per cell before it becomes unusable). This effect is readily visible with USB memory sticks that use TLC and have low numbers of total drive writes (often in the order of 100 DW) before the stick becomes unusable.

    With QLC I wonder how many total drive writes will be possible before the performance drops.

    I personally much prefer dependable memory rather than slightly cheaper memory. (My main system has a 960 Pro as the system drive!!)

    1. Naselus

      Re: Endurance ?

      Came to make the exact same comment

    2. joed

      Re: Endurance ?

      Exactly, I've been trying to avoid TLC crap and now it'll be premium over QLC (while MLC will go the way of SLC).

  2. Ken Hagan Gold badge

    "We can't call it quintuple level cell because QLC is already used for quad-level cell flash. "

    You'll hit that with 6 and 7, too. Might I make a suggestion? Writing 2LC, 3LC, 4LC, 5LC ... works fine for the forseeable future. Start using it in articles now and hope that it catches on with other authors before the quad-quin ambiguity becomes a real problem.

  3. Steve Knox

    Diminishing Returns

    Imagine 5 bits/cell flash ... That would be a 25 per cent increase over QLC flash, 5 bits instead of 4.

    Yeah, but QLC would be a 33.3% increase over TLC, and TLC was a 50% increase over MLC, which was a 100% increase over SLC.

    Adding levels to a flash cell increases capacity at a diminshing rate, at the cost of increasing the odds of an error at a rising rate. 3D NAND mitigates, but does not eliminate, the error cost. It does nothing for the diminishing rate of return.

    1. Naselus

      Re: Diminishing Returns

      Presumably they'll attempt to over-provision even more prolifically than they presently do. Whether this will deliver an increase in total capacity with acceptable endurance is an open question, however; at some level-per-cell, it'll cross over and start to reduce total drive capacity due to the level of over-provision required to maintain serious endurance.

    2. Anonymous Coward
      Anonymous Coward

      Re: Diminishing Returns

      It provides 33% increase in raw bits, but if you are using some of them for additional error correction and others for additional overprovisioning it may not add all that much. The case for "5LC" would be even worse, should they ever think about doing that.

    3. JeffyPoooh

      Re: Diminishing Returns

      The poorly chosen "nLC" nomenclature (see other post) assumes that the number of voltage levels (or steps) must be a power of two.

      Poor nomenclature leads to affected thinking.

      In fact, it's very likely that an intermediate number of voltage levels, such as 10 or 17, might be more feasible than skipping from ...4 to 8 to 16 to 32... Then you'd contain fractional bits in each cell, which would have to be recombined by the control circuit.

      I trust that this is obvious.

      1. Anonymous Coward
        Anonymous Coward

        Re: Diminishing Returns

        Fractional bits because you can't make a power of two jump mean even tinier increases coupled with everything being more complicated. I see zero chance of that ever happening.

        1. JeffyPoooh

          Re: Diminishing Returns

          DougS, "Fractional bits...mean even tinier increases..."

          No. Not necessarily. It might mean the opposite.

          Fractional bits means being able to optimise the voltage steps, and then accepting as many bits (including fractional bits) as can be represented by that number of voltage steps. Fractional bits (per cell, like 3.7 or 4.3 bits per cell) is another way of saying some bits are effectively spread over several cells. Requires circuits to extract and recombine, raw data (as distinct from error correction).

          They're saying that "QLC" are now more feasible with the additional of error checking, which is certainly a "Well duh" invention. Quad (4) "Level" (sic) Cells implies 16 voltage *levels*, representing Quad (4) *BIT* Cells. The next mindless step would be "5LC" (sic), which implies 32 voltage levels. But that assumption is dumb, and traceable to the dumb nomenclature which implies power of two voltage steps.

          My basic point is that there's no reason to assume that the optimum number of voltage levels is going to be 8, 16, and 32. It might be 10, or 17, or 23. The optimum number of voltage levels will change over time (with progress) and (of course) is related to other design decisions.

          If you're not following, then re-read all my posts on this topic.

          PS: This concept of fraction bits is very basic and as old as the hills. I'm not suggesting anything new, I'm just here to grumble about the daft nomenclaturism, e.g. "TLC" (sic), and to hopefully correct the thinking of anyone so affected.

          1. Toastan Buttar

            Fractional bits are pure madness

            Using an integer number of bits per cell already leads to inefficiencies.

            For example, in order to read a random page of data from a 3BPC flash device, the controller firmware has to perform the following steps:

            1. Read the wordline at 3 different comparison levels

            2. Store these intermediate wordlines in RAM

            3. Perform a series of Boolean logic functions on the intermediate worldines to extract the noisy page of data and its noisy ECC bits.

            4. Combine the noisy page and ECC data to extract the original, uncorrupted written data.

            If your storage system spreads the ECC data between the three stored pages, then you must read the entire wordline at 7 different comparison levels in step 1. Store 7 intermediate wordlines in RAM. Perform 3 times the number of Boolean logic functions that you did in step 3 to extract all three noisy pages of data and ECC bits. Combine all three pages of noisy data and ECC to extract three uncorrupted pages as written initially.

            Extending this to fractional numbers of bits per cell would necessitate reading MULTIPLE WORDLINES at MULTIPLE THRESHOLD LEVELS and applying bizarre Boolean logic functions to extract your noisy data+ECC pages. This ignores the complex maths involved in applying something like BCH to generate ECC in a fractional bit scenario. Yes, it's possible in theory, but in practice it's ugly beyond belief. The complexity (and hence cost) that this would add to firmware design and testing would swamp any possible gain in storage.

            In short, you'd have to be certifiably insane to propose introducing fractional bits to commercial NAND devices.

  4. JeffyPoooh

    The tragic N "Level" Cell misnomer

    El Reg wrote, "TLC (3bits/cell)" and "QLC (4bits/cell)", using the erroneous but industry standard nomenclature.

    The Three "Level" Cell (TLC) stores three bits per cell, which implies *EIGHT* different voltage LEVELS. In other words, Eight (voltage) Level Cells (semantically "8LC") gives you three BITS per cell. Similarly, the Quad "Level" Cell (QLC) stores four bits per cell, which implies 16 different voltage levels.

    Whoever chose the word "Level" to go in the middle of the nLC acronym made a dumb mistake.

    We'll survive. So carry on.

    1. really_adf

      Re: The tragic N "Level" Cell misnomer

      Three and four levels is at least useful. With a Single Level Cell, how do you store any data? :)

      Genuinely, why is SLC called that? The only thing I can think of is that it refers to writing, not reading or erasing.

  5. Toastan Buttar

    "Genuinely, why is SLC called that?"

    Possibly because there was a single /threshold/ voltage comparison level to determine whether a cell represented a '0' or '1' on read.

    MLC (for 2 bits per cell) covers the use of three comparison levels to fully decode two stored pages.

    This however does not justify the extension of the nomenclature to TLC for 3-bits-per-cell technology.

    Why the industry didn't just call it BPC (Bits-Per-Cell) from the beginning, I'll never know.

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