The 'F' designated processors with a UPI socket on the processor package are particularly interesting.
Intel bolts bonus gubbins onto Skylake cores, bungs dozens into Purley Xeon chips
Intel has taken its Skylake cores, attached some extra cache and vector processing stuff, throw in various other bits and pieces, and packaged them up as Xeon CPUs codenamed Purley. In an attempt to simplify its server chip family, Chipzilla has decided to rebrand the components as Xeon Scalable Processors, assigning each a …
COMMENTS
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Wednesday 12th July 2017 06:34 GMT Ken Hagan
Re: What's old is new again...
In fairness, the scheme offers nothing new in functional terms, because the CPU has no notion of thread as distinct from process, so the existing page protection mechanisms could always have been used to do this. What's new is that Intel reckoned that resurrecting a much more primitive scheme (costing only one register per thread) was worth it at this point in time.
No doubt the cycles of reincarnation will continue and this will soon be "legacy cruft, used by only one or two programs ever, but still needing to be implemented by every processor they ship, now and forever". Then, in about 20 years time, Intel will finally drop support for it and everyone will be aghast, ranting about the back-compat implications.
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Wednesday 12th July 2017 06:18 GMT diodesign
Re: Not mentioned the support for NVDIMM
There was no mention of NVDIMMs by Intel in the tech materials its engineers shared with El Reg, so I guess this has been paused?
I must confess, I'm a software and CPU dude, not a storage person, so I didn't pick up on this. I've let my colleague Chris Mellor, our storage writer, know so he can follow up.
C.
(The other Chris)
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Wednesday 12th July 2017 06:25 GMT John Smith 19
"annoyingly titled Innovation Engine: "
The "Innovation" being that it won't allow you access with a blank password?
That it wasn't bought in from another mfg without any penetration testing at all?
That this time it was designed in house and Intel reviewed the code?
What I'd have liked was a summary diagram of range of CPU/ chip. # of ports between CPUs and caches, # of ports off chip to main memory array.
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Wednesday 12th July 2017 07:28 GMT Steve K
SImplification
As mentioned in the article, I don't see how this reclassification simplifies anything over the old classification...
The Intel Ark site - since its redesign - also goes out of its way to make it difficult to compare processor features/specifications due to its perverse layout, I actually found myself using the Wikipedia Xeon page to look up current Xeon specs the other day rather than Intel's site
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Wednesday 12th July 2017 08:59 GMT Anonymous Coward
Is it any coincidence that this has come along just when AMD have started looking good again? Has Intel had this in their back pocket, unmarketed, for a rainy day, depriving customers of an earlier opportunity to get this kind of thing, generally wasting their time?
Oh boy is it time for there to be some strong competition...
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Wednesday 12th July 2017 11:51 GMT John Smith 19
"Is it any coincidence that this has come along just when AMD have started looking good again?"
Depends how long this has been planned for.
Different industries and businesses have different cycles for this, usually timed around either key trade shows or conferences or the end of their financial years.
The Powerpoints may have been ready for months. However if the physical event was done in a hurry that would suggest Intel was reacting to something in a hurry, but it's not clear from the article how hastily it was set up.
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