New Azure servers to pack Intel FPGAs as Microsoft ARM-lessly embraces Xeon

Microsoft may have said ARM servers provide the most value for its cloud services back in March, but today it's given Intel's new Xeons a big ARM-less hug by revealing the hyperscale servers it uses in Azure are ready to roll with Chipzilla's latest silicon and will all use Chipzilla's field programmable gate arrays. Those …

[John Smith 19]

And the Bromance rolls on......

It's like an old couple renewing their wedding vows.

Although the couple I always think of in this context is Mickey and Mallory Knox.

Meanwhile it looks like Google has taken over NCR's old role as "First customer" outside of Intel to use new chips.

[Tom Samplonius]

Re: And the Bromance rolls on......

" And the Bromance rolls on...... It's like an old couple renewing their wedding vows."

The Wintel alliance is over. Apple, Google, Amazon, and Microsoft are the top 4 direct purchasers of Intel CPUs. Intel just needs to keep delivering marketable features at a cost that is less than these four could build their own CPUs. And manage the roll-out in some way, as everyone wants to launch the new feature first.

[Voland's right hand]

Left hand does not know what the right hand does

Business as usual in an organization this size. They are always a bit schizoid.

[Ken Hagan]

So today's news is that MS are interested in a device that sits alongside the CPU and offers potentially huge speed-ups for certain classes of compute-intensive problem. That was, of course, also the news about 20 years ago. What eventually panned out was that MS (and others) abstracted the interface to such devices, so that programmers could use the feature without (mostly) caring about which vendor was providing the gizmo. I expect this will go the same way. AMD are doing the same sort of thing, aren't they? Next month's news will therefore be that Intel no longer have the market to themselves and MS (and others) don't care one way or the other because their APIs work on both.

So, yeah, nice to see the technology roll out, however slowly. Not a reason to rush out and buy more Intel shares, though.

[CheesyTheClown]

Not entirely true but mostly

Alters has been hard at work on reconfigurable FPGA which is exciting. Consider this, calculating hashes for storage is simply faster in electronics, as fast as the gate depth will allow. Regular expressions are faster, SSL is faster, etc...

The problem is, classically, an FPGA had to be programmed all in one go. If Microsoft has optimized the work flow of uploading firmwares and allocating MMIO space to FPGAs and Altera has optimized synthesizing cores and Intel has optimized data routing, the a web server could offload massive work loads to FPGA. Software defined storage can streamline dedup and compression, etc...

This made perfect sense.

[John Smith 19]

"Not a reason to rush out and buy more Intel shares, though."

TBH I'm looking forward to the day of the one atom thick oxide layer transistor.

And the realization that the entire digital semiconductor industry will have to pivot into a new direction to increase density since "device shrink" literally no longer exists. *

*Unless someone figures out how to "engineer the electron transition levels of individual atoms," provided someone figures out what that phrase even means.

[John Smith 19]

"Look forward no longer, it's getting there..."

Let me translate that report for you.

"Some grad student has, eventually, managed to produce a sample of ZnO on Graphene that lasted long enough for them to test it." Does that sound production ready to you?

In the context of conventional Silicon based semiconductors the key oxide layer that matters is the Silicon Oxide layer on the surface of the chip between the gate conductors (whatever they happen to be) and the chip surface. It's not a semiconductor, it's an insulator. Its thickness is typically 1/10 the line width of the chip. Making a pinhole free layer of this across a surface about the size of a carpet tile (and rising) is another key problem as you go to "EUV" lithography (or soft X-ray as they used to call it, until they realized it make PHB types too nervous).

"Also, your post shows that you're intelligent, but not experienced. "

That's quite flattering.

Yours suggests you don't parse English quite as well as you think you do (but then I was taught English by someone for whom it was not a first language). "Getting there" <> "there". I'm fully aware of stacking wafers to make 3D chips. My post was carefully written only to point out increasing density by a "process shrink" would no longer be an option to increase density.

At that point stacking stops being a case "if process development is a bit slow we'll just stack a couple of chips till its ready" to being the only way to increase density.

Given the heat output of modern processors is already greater than the equivalent heat rating of the re-entry heat shield on the Apollo capsule stacking them up is going to pose some tough problems, as Silicon is not that good a thermal conductor and the wafer thickness is about 30x the actual electrically active layer thickness.

Multi layer memory devices can be structured so only one layer is active at a time, but what would be the point of having X layers of processors when you can only have one active, otherwise the stack melts?

Although I'm sure the Intel Marketing department would find a way to sell such a device.

[MT Field]

Sounds great!

I bet that looks cool on a Powerpoint slide, and its a great way to "leverage" technologies. Until you try and use it, when it all turns to, erm, something less than useful. So I think this is all hot air and money down the drain, but we'll see.