Toshiba, Western Digital put away lawyers long enough to play 96-layer 3D NAND game of Jenga

Just as we are getting used to 64‑layer 3D NAND chips, along come the warring flash joint-venture couple Toshiba and Western Digital. The pair say their JV has produced a 96‑layer prototype die, with Toshiba also introducing four-level cell tech. A 96‑layer 3D NAND chip has 50 per cent more layers than a 64‑layer chip, and …

[Anonymous Coward]

Failure Modes

Endurance really isn't an issue, most of my 14 TB+, and growing, might as well be etched in stone. And yes, M-Disc has always been on my really would love to have list. Any problems that I forsee here revolve around pri e point and that SSD's fail completely with no warning. Still. That's why NAS disks feature here.

So, Tosh-WD, what's those gonna be?

[JeffyPoooh]

Misnomer Alert

"3-Level Cells" = 3‑bits/cell, that is 8 Levels

"4-Level Cells" = 4‑bits/cell, that is 16 Levels

To be pedantic, storing 3 bits per cell requires eight (voltage) 'Levels'. Storing 4 bits per cell requires sixteen (voltage) 'Levels'.

Somebody screwed-up this 'Levels' nomenclature at the outset of this MLC technology.