Re: FPGA
"In theory an FPGA "could" be reconfigured at run time, rather than as a field upgrade."
Xilinx reprogrammable SRAM FPGAs had reference designs when they came out in the mid-1980s. One was revolutionary as it reloaded between the transmit and receive phases on a serial line.
A networking product in the late 1980s had several possible Xilinx FPGA download images available in the box - each one expressed particular options that the management station selected. This made it very efficient as the FPGA didn't have unused modes taking up space that would have required a more expensive chip.
A piece of test gear in the late 1980s overcame the limitations of the then Xilinx maximum gate counts by run-time "compiling" of the FPGA download image to modify certain preset features. That set up user configurable timing counters and test conditions etc.
Those examples were in the infancy of the reprogrammable FPGA. Over the last 30 years FPGAs' capabilities have grown enormously as the gate counts have increased by several magnitudes. They now have partial reloads while running - and enough gates to include an embedded cpu function as part of the on-board capability.
The challenge has been to describe a language that allows an FPGA function to be expressed as dynamic changes to algorithms when doing data processing in a main processor.