I like it - more detail needed please.
Uses standard PHYs, I assume they mean SERDES,
Well that means point to point links, and switches rather than the bussed architecture in the slide deck.
But switches will add latency.
So no root complex like PCIe, or connection via non transparent bridges?
Works with unmodified OS.
So I'm guessing it doesn't properly support hot plug / unplug then. Because standard OSes don't take kindly to having their memory maps shifting beneath them like sand in the wind.
I hope that hot plug gets integrated properly. Sounds like a very interesting project. If any of the cooperating partners are looking for a hardware development engineer with 20+ years experience designing storage systems, there's a very good chance that I'll be laid off today and this sounds like an exciting project.
[/hopeful shot in the dark]