back to article StoreServ's ASIC architect must have one heckuva crystal ball

StoreServ arrays use special hardware, an ASIC, to accelerate storage array operations, and this is redesigned for each major generation of the arrays. The current design is generation 5. Siamak Nazari is an HPE fellow and StoreServ architect, and is heavily involved in the design of the forthcoming gen 6 ASIC. An ASIC design …

  1. Anonymous Coward
    Anonymous Coward

    5 year cycle

    is an eternity by today's standards and if you miss the mark you're in major trouble. It is precisely why ASICs are yesterday's news.

    More cores, cheaper memory and optimized SW functions are the answer.

    HPE is stuck in 1999

  2. damnyankee

    ASIC halves CPU alright

    I would hope the ASIC more than halves necessary CPU utilization, as they essentially take a 2 socket system, run 1 socket and 1 ASIC. This halves their PCIe lanes, and their CPU core counts.

    If the ASIC does 800MBps, and a xeon core does 150MBps... you come out ahead with >6 core Xeon. Given there are 22/24 core Xeons now, this particular spec does not pan out in their favor and is not something I would advertise overly much

  3. damnyankee

    ASIC halves CPU alright

    if 1 ASIC does 800MBps, and 1 Xeon core does 150MBps, then the ASIC does not come out ahead in that calculation. There are at least 22 core Xeon chips (maybe 24?). The break-even point is 5.3 cores.

    I wouldn't advertise that particular metric if I were HPE. Not to say there aren't other advantages to the ASIC, but the cited numbers don't look good for them ot anyone with the ability to multiply.

    1. Nate Amsden Silver badge

      Re: ASIC halves CPU alright

      It's not as if they have no CPUs. Their gen 5 high end flash box has 128 2.5ghz xeon cpu cores and 16 ASICs (across 8 controllers) sitting next to 3,500GB of cache.

      It's rated for 75GB per sec reads and around 30GB per sec writes(to/from servers), posted good SPC2 numbers a while back no SPC1 yet though. It will get faster in the future as the software is optimized further for the Gen5 ASIC.

      Controller diagram

      1. damnyankee

        Re: ASIC halves CPU alright

        Of course. I was just pointing out that based on the numbers they provided, the ASIC comes out behind a high-core Xeon. Those numbers could be wrong, or need to be revised, or don't take into account the full picture, but their "ASIC=X MBps, Xeon=Y MBps" math means pretty much any Xeon would be superior to the ASIC, and if I were HPE, I wouldn't be citing those numbers as a positive because if you can multiply you go "wait a minute..."

  4. Joerg

    "He characterises a XEON core as having 150MB/sec bandwidth." WHAT ? What ancient Xeon is he talking about?

    1. Anonymous Coward
      Anonymous Coward

      "He characterises a XEON core as having 150MB/sec bandwidth." WHAT ? What ancient Xeon is he talking about?

      Maybe it comes down to small block I/O thoughput rather than a MB/s throughput rating, 20,000 IOps per CPU core @ 8K translates to 156MB/s which doesn't sound too unreasonable for a real world workload.

  5. Mike_in_the_house

    Vision from Visionaries

    Yes, and with a visionary like Mannish that's going to go far, was he not the guy that said that flash would not become mainstream in his previous company?

  6. Alex McDonald 1

    Ah, ASICs. So last century

    I feel like I'm back in the 1950s, with valves and relays. Nostalgia.

    Unless these things can seriously reduce latency in the IO path, they're boat anchors. Getting n times the bandwidth is easy; have n servers. Getting n/10 latency is hard.

    1. Anonymous Coward
      Anonymous Coward

      Re: Ah, ASICs. So last century

      Well it seems Intel actually agree.with the need for ASICs.

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