The fact that it is possible to trigger bit flips by row-hammering shows again that DRAMs are not perfect. The databits in DRAM memory are stored charge-based and this charge can only be kept for a few milliseconds, then needs a refresh by the CPU.
It is well-known that DRAM memory is sensitive to any kind of disturbance and row-hammering is just one of them. Also antennas, radiation or heat can cause bit flips. Many bit-flips happen without being able to find a root cause. The older memory chips get, the more they degredate and the more sensitive they become. It's interesting to see that brandnew devices work flawlessly for a while and then have the first "hiccups".
Some people say that shorter refresh-cycles would help, but this is only partially true. Many bit-flips are not related to the data-retention time of the memory cells, but come from external disturbances. In addition, more-frequent refreshing would result in higher power consumption and a strong performance drop (the DRAM can not be read or written during a refresh-cycle).
Any electronic device we own, if it is a smartphone, a WiFi router, navigation system, settop box or our PC and laptop, sometimes has a malfunction or crash and needs to be rebooted. We got used to that and don't really think about why it happened.
Now look at an ECC protected system like a server and you find it never crashes although it stays switched on for months and years. Why is it so much more reliable although the software running on it is fairly similar to that running on a PC or laptop? It is the ECC error correction that covers bit-flips in the DRAM.
And yes, Wifi Routers run their software from a DRAM, also most other electronics use DRAMs. Even a HDD or a SSD drive uses a DRAM as a cache or write-buffer. Bit-flips modify the data or the software code and result in random fails or even crashes.
But how can we add ECC to systems that normally do not support ECC?
The ECC error correction is normally performed by the CPU which generates additional parity-bits for all data it writes to the DRAM. Upon reading the data and the parity bits from the DRAM, the CPU performs the ECC algorithm and can detect&correct bit-flips.
Not only the CPU needs to be ECC-capable for that, but also the DRAM memory bus needs to be wider. Instead of standard 64 bits width, 8 additional parity bits are required, so the memory must be 72 bits wide. Talking in "DRAM chips", that normally means to have minimum 9 DRAM Chips! Modules with 9 DRAM chips (or 18 or 36) might fit into a PC or laptop, but definitely will not fit on a HDD, SSD, router or other small form factor electronics.
But now there is something new: DRAM memory chips with on-chip integrated ECC error correction (www.intelligentmemory.com/ECC-DRAM/)
This could solve the problems as no more ECC-capable CPUs are required to use them. And even if some products (HDD/SSD/routers, etc) use just one single DRAM chip on them, they could take such an ECC DRAM and have the required protection.
The ECC DRAM chips are fully compatible to conventional DRAMs, so they fit everywhere. They can even be put onto a standard 64 bit wide laptop or PC memory module PCB and would result in self-correcting Non-ECC modules. Each chip on the module will verify and correct its output-data by the integrated ECC function.
Biting the hand that feeds IT
