back to article HGST brings PCM to flash show, stuns world+dog with 3 million IOPS

In a terrific demo of the wrong technology for the Flash Memory Summit, HGST is showing a PCIe-connected Phase Change Memory device running at three million IOPS with a 1.5 microsecs read latency. Phase Change Memory (PCM) stores binary digits as differing resistance levels by changing the state, or phase, of the chalcogenide …

  1. Anonymous Coward

    TLA's got to love them..

    and there was I wondering how on earth Pulse Code Modulation was going to work in a flash drive.

  2. Slap

    As much as I agree it's not flash

    As much as I agree it's not flash storage I think the word "flash" has slowly become synonymous with any form of solid state storage, even though we're not in a post "flash" world yet, and will still be used for new solid state storage technologies.

    Think of it from the users perspective - flash means fast (for some it still means Brian Blessed bellowing "Gordons alive?"). The users don't know the tech behind it and thus any form of storage that's fast and not spinning is flash to them.

    Wrong show, but perhaps the right place to demonstrate a post flash technology anyway.

    1. Charles 9

      Re: As much as I agree it's not flash

      Perhaps, though if you're gonna crash such a party, you'd hope to bring something a little more surprising (you know, a "this changes everything" surprise). The read numbers are good but the write there's the question of longevity, which is another issue with Flash RAM, especially with longer times and higher activities.

  3. Stuart Halliday

    5Gbits? Only 5 measly Gbits...?

  4. Deckard_C

    According to the paper the prototype used 5 Gbit which was built using a prototyping platform which uses a FPGA and happens to use LPDDR2-NVM to talk to the PCM on a dimm . This system sits in it's own box outside of the server connected by PCIe over cable to the server. So full length PCIe demo card is probably a FPGA plus a whole load of PCM chips. The FPGA may need a big heat sink as the one in the prototyping platform did, but they may be using a different smaller FPGA for the card?

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