Future of storage: Micron bets chips on 3D NAND flash – but NOT YET

As far as the world's number two DRAM chip-maker is concerned, 2D or planar NAND can go through another lithography cycle before 3D techniques may become necessary because a two-year-old NAND design change has enabled Micron to scale its lithography down to 16nm and maybe beyond. El Reg interviewed Glen Hawk, Micron's VP for …

[Anonymous Coward]

Remedial math

"For example, Micron's M500 client SSD uses 20nm NAND and has capacities between 120GB and 960GB. We'd assess that this could simply double with 16nm parts, meaning a 240GB to 1.92TB range."

Can someone indicate how 20nm to 16nm will enable a doubling of capacity for SSDs?

[Geoff Campbell]

Re: Remedial math

The difference is 20% in each of two dimensions. Imagine a square of size 20cm, and another of 16cm, and you will see that the latter is not much over half the size of the former - 256 square cm vs 400 square cm. Thus, increase the size of the NAND chip by a very small amount, and you get twice the number of cells per chip.

GJC

[nkm]

Re: Remedial math

You could fit 50x50=2500 20nm features into a μm^2, and 6.25x6.25=3906 16nm features. I make that 56% more, you'd need to drop to 14 to double the density of 20.

If you're assuming that it's a true 3D stack then fair enough (125K v. 244k / μm^3), but that would imply you're reducing the die depth at the same time as feature size.

Is that the case? I'm not a wafer expert.

[Nigel 11]

No ReRAM?

Pity nothing asked about ReRAM (Memristors). When do they see it becoming a competitor with Flash? Are they planning to manufacture it? Etc.

[circuitguy]

heat issues

Although the engineers have done good work here, I worry about hot spots that can create uneven expansion in 3d space. At this level, a few molecules breaking free can be problemic, especially if they are ionized from breaking away their lattice frame.