back to article Unisys pumps up ClearPath mainframes with Xeon E5s

Unisys has been on a quest to get out of designing processors for its ClearPath mainframes and porting its MCP and OS 2200 operating systems from its respective Libra (Burroughs) and Dorado (Sperry-Univac) machines to Intel's Xeon processors for almost as long as Intel has been serious about the server racket. And, with the …


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  1. P. Lee

    Cheaper, but better?

    Your software might be great, but what if HP comes along and lashes x86 hardware together with the same IOPS? You no longer have the skills to design new cpus that are better than what HP can put together. You're on a more even playing field, with only the interconnects and software to differentiate.

  2. Ilgaz

    The genius is OS itself

    First release 1961, contains (kinda made possible by) Knuth's code as student.

    When you have time, read

    Nothing gets more interesting and unique than that. Being able to run on xeon isn't possible without the initial design of it back in 1961.

    1. Anonymous Coward
      Anonymous Coward


      ...what is it about the MCP design which made it possible to run on Xeon? The OS 2200 (nee OS 1100 and Exec 8) shared few of the MCP design characteristics but has been emulated on Intel for decades.

      1. Ilgaz

        The language

        OS itself is written in high level language. Industry loved the idea but thought it is impossible to do it.

        Knuth as student, during his summer break, made it.

        All they need is a decent compiler for target cpu.

  3. Kebabbert


    "...The Libra 4280, which has perpetual pricing, spans from 50 to 2,400 MIPS, while the Libra 4290 offers from 30 to 1,680 MIPS with a ceiling of 2,400 MIPS peak if you have a sudden spike...."

    Emulation of an IBM Mainframe gives 3.200 MIPS on a 8-socket Nehalem-EX server.

    1. David Beck

      Re: Emulation or Simulation?

      Emulation, actually we are talking about simulation here as the firmware in the Intel chip is untouched and all of the work is done by x86 instructions not firmware instructions, is much simpler for the base S360 (little changed since the 1960's) architecture.

      MCP runs natively on 48bit word machines with hardware typing per word, S360 is 32bit untyped. This means it's perfectly acceptable to do integer instructions on character strings on a S360 machine and impossible to do so on the MCP machine. So there must be a "type byte" per word holding the typing info referenced by the execution simulation for each instruction.

      The Univac case is a bit more complicated as the base architecture is IBM 7000 series (the one that preceded S360) and uses 36bit words and, interestingly, 1's complement binary arithmetic. That's the one that has two representations for zero (plus and minus).

      Both of these represent considerable barriers to fast simulation since there is a mis-match at the fundamental storage architecture. I've looked but been unable to find any papers on how these problems were overcome.

      S360/370/Z all share the same base storage architecture, 32bit words, two's compliment arithmetic, which is shared with the x86 family as well. I'd be very surprised if a simulation of S360 was not considerably quicker than either of the Unisys architectures.

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