SPARC features ...
... were reasonably well thought-out when the architecture was designed; but since you're comparing it with ARM (not a good comparison,what do electric bikes and humvees have in common ?), I'd like to comment a bit on that.
ARM have continuously evolved / improved their core instruction set (ARMv5 -> v6 -> v7, all adding quite generically-useful things), and that even though few people would call ARM's initial instruction set design anything else but "great". ARM and its licensees also take hardware advances (caches, builtin ram, close-coupling between CPU and devices) and continuously incorporated such into the implementations. Anyone can _see_ how ARM leads when it comes to CPU instruction set design / improvement, or, to phrase it differently, achieving the "speedy potential".
SPARC is the monolith of instruction sets, though - set in dark, menacing, impressive stone since sparcv9 was concocted (1994 ?). Some of the things SPARC does (branch delay slots, /dev/zero register, ASIs, the instruction set extensibility) are indeed useful. Others - fixed-size register windows, or even the windowing mechanism as a whole have proven to be more of a burden; they make SPARC programs use larger stacks and therefore require comparatively larger caches to achieve full potential. Then there's Sun insistence over decades not to consider out-of-order implementations, even at a time when Fujitsu's SPARC64 had already proven the usefulness (fortunately, the T4 finally addresses that). Also, again in comparison with ARM (or x86), SPARC machine code isn't very dense - larger code footprint, again needs bigger cache / cache bandwidth. There would be ways to address that (like x86's micro-ops caches), so agree with your assessment "speedy potential", yet a lot of that remains unexploited.
Also, very unlike ARM where there are a variety of widely-used instruction set extensions that ARM keeps on improving regularly, SPARC has not had any updates on that front for a while either. Yes, the T-series have the crypto accelerator as closely-coupled device, but that's as far as it went. Not every design considered "great" will keep that label over time; at least from my point of view ARM has done better there than SPARC.
SPARC is great because it's reliable, got very predictable behaviour, runs all your old stuff.
But SPARC has had great potential in the 80's, had great potential in the 90's, has been having great potential in the naughties and still has great potential ... and it will always have great potential.
Fingers crossed for the T4; some achievement instead of potential would be wonderful.