Re: the same results. Every time
"Microprocessors are not magic. If you get them into a known state, and feed them a given set of inputs at given points in time, they will give you the same results. Every time."
Microprocessor systems are not always perfectly designed or implemented, and even if they were, they may not be 100% predictable especially once you move outside the core itself and into chip level and system level components and behaviours, e.g. caches, DMA capability, etc.
E.g. where do things like soft errors in caches fit into the picture of perfectly predictable timing? They don't, not for people (such as safety criticial systems people), who take their behavioural and timing analysis seriously. Obviously that makes life inconvenient for Der Manglement in these cases 'cos it means that they're not able to justify using widely used chips and technologies which rely on cache, OOE, etc. Not without having to handwave quite a lot anyway..
A soft error on something that was in cache (resulting in a forced cache miss) is routine expected behaviour, it's inevitable that they will happen, they just can't be predicted in terms of when they will happen. When it does happen, the visible timing of the system may be different than it would without the soft error. That timing difference may then propogate in an unmodellable way, rendering any system-level timing predictions largely irrelevant.
A bit like the butterfly/chaos effect, except not as pretty.
DMA transactions may have similar effects on timing predictability.
Here's one prepared earlier for the FAA, from their "Handbook for the Selection and Evaluation of Microprocessors for Airborne Systems " at
"Nondeterminism arises because the availability of a shared resource becomes largely dependent on the run-time behavior of other processes sharing the same resource. In many cases, the run-time behavior of programs is data-dependent and cannot be predicted offline."
"Out-of-order instruction execution or dynamic scheduling of instructions may cause timing anomalies. For instance, when there is a cache hit, an instruction takes longer to execute than when there is a cache miss, contrary to popular knowledge that cache hits take less time. For example, in a processor that employs out-of-order execution, a cache miss will allow subsequent instructions to begin execution. This out-of-order behavior may lead to a reduced execution time for a set of instructions. This makes the worst case execution time of tasks hard to predict."
Mostly this doesn't matter. Sometimes it does. Handwaving doesn't make it go away, proper design and analysis might make it less dangerous.